AD9650 Analog Devices, AD9650 Datasheet - Page 8

• Manufacturer Part Number: AD9650
• Description: 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9650

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 105MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p,2.7 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9650
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
1
Timing Diagrams
See Figure 93.
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CH A/CH B DATA
CH A/CH B DATA
DCOA/DCOB
DCOA/DCOB
CLK+
CLK–
CLK+
CLK–
1
V
V
IN
IN
Conditions
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge
N – 1
N – 1
Figure 3. CMOS Interleaved Output Mode Data Output Timing
t
t
CH
CH
Figure 2. CMOS Default Output Mode Data Output Timing
t
DCO
N – 13
t
t
PD
PD
N
N
t
t
N – 12
t
t
CH A
A
A
CLK
CLK
t
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DCO
t
N – 12
SKEW
t
SKEW
N – 12
CH B
N + 1
N + 1
N – 11
CH A
N – 11
N – 11
CH B
N + 2
N + 2
N – 10
CH A
N – 10
N + 3
N + 3
N – 10
CH B
CH A
N – 9
N – 9
N + 4
N + 4
CH B
N – 9
CH A
N – 8
N – 8
N + 5
N + 5
Limit
0.3
0.40
2
2
40
2
2
10
10
10
10
Data Sheet
Unit
ns typ
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min