AD9963 Analog Devices, AD9963 Datasheet - Page 22

• Manufacturer Part Number: AD9963
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9963

• Resolution (bits): 12bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 12x2-100 MHz
• Dac Bits X #dacs-clkspeed: 12x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

AD9961/AD9963
Table 13. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
DS
DH
CLK
S
C
HIGH
LOW
DV
SCLK
SDIO
CS
DON’T CARE
DON’T CARE
SCLK
SDIO
CS
A0 A1
Timing (Min, ns)
5.0
5.0
20.0
5.0
2
10
10
5.0
A2
A3
A4
16-BIT INSTRUCTION HEADER
t
t
Figure 37. Serial Control Port Access—LSB First, 16-Bit Instruction, Two Bytes Data
DS
S
A5
SCLK
A6
SDIO
SDO
CS
A7
BIT N
Figure 36. Timing Diagram for Serial Control Port Register Read
A8
t
HIGH
A9 A10 A11 A12
t
DH
Figure 38. Serial Control Port Timing—Write
Description
Setup time between data and rising edge of SCLK.
Hold time between data and rising edge of SCLK.
Period of the clock.
Setup time between CS falling edge and SCLK rising edge (start of communication
cycle).
Setup time between SCLK rising edge and CS rising edge (end of communication
cycle).
Minimum period that SCLK should be in a logic high state.
Minimum period that SCLK should be in a logic low state.
SCLK to valid SDIO and SDO (see Figure 36).
DATA BIT N
t
CLK
t
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DV
t
N0
LOW
N1
R/W
BIT N + 1
DATA BIT N – 1
D0
D1
REGISTER (N) DATA
D2
D3
D4
D5
D6
D7
D0
REGISTER (N + 1) DATA
D1
D2
D3
t
C
D4
D5
D6
D7
DON’T CARE
DON’T CARE