AD9963 Analog Devices, AD9963 Datasheet - Page 26

• Manufacturer Part Number: AD9963
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9963

• Resolution (bits): 12bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 12x2-100 MHz
• Dac Bits X #dacs-clkspeed: 12x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

AD9961/AD9963
Register Name
FIFO Alignment
FIFO Status
Tx Scale P
Tx Scale 0
Register
Address
0x33
0x34
0x35
0x36
Bit(s)
3
2
1
0
7
6
5
4
3
2:0
7:0
7:5
4:0
7:5
4:0
Parameter
RXCLK_INV
RXIQ_HILO
RX_IFIRST
RX_BNRY
Unused
FIFO_INIT
Aligned
ALIGN_ACK
ALIGN_REQ
FIFO_OFFSET[2:0]
FIFO_LVL[7:0]
Unused
SRRC_SCALE[4:0]
Unused
INT0_SCALE[4:0]
Rev. 0 | Page 26 of 60
Function
11: RXCLK is driven by the DLL output.
Note that the RXCLK signal is present on the TRXCLK pin with one
exception. In Half-Duplex 1-Clock mode, the RXCLK signal is present on
the TRXCLK pin when Rx is active, but the TXCLK signal appears on the
TRXCLK pin when TX is active.
0: uses TRxCLKIO negative edge to drive out Rxdata.
1: uses TRxCLKIO positive edge to drive out Rxdata.
Data appears on the RXD bus sequentially but is sampled in the Rx path
in pairs. RXIQ_HILO selects how the RXIQ signal marks each data pair.
0: each data pair is marked by RXIQ being low then high.
1: each data pair is marked by RXIQ being high then low.
The Rx path I and Q ADCs sample simultaneously producing a pair of
samples. Because the RXD bus is shared, the sampled I and Q data
appears on the TRXD bus sequentially. This bit determines the order of
the paired samples.
0: Q appears first on Rx path.
1: I appears first on Rx path.
0: twos complement on Tx path.
1: straight binary on Tx path.
1: FIFO read and write pointers are aligned after chip reset.
1: FIFO read and write pointers aligned after frame input driven FIFO reset.
1: FIFO read and write pointers aligned after serial port driven FIFO reset.
1: request FIFO read and write pointers alignment via serial port.
Sets the FIFO read and write pointer phase offset following FIFO reset.
Normally this should be set to 4 to set the FIFFO to half full.
000 = 0.
001 = 1.
…
111 = 7.
Indicator of the amount of valid data in the FIFO. Each one indicates a
latched input sample in the FIFO. Ideally, the eight deep FIFO should be
half full, indicating four latched input samples. The indicator is a
thermometer code that can wrap around from LSB to MSB. Some
examples follow:
00011110: indicates that FIFO is half full. The read pointer is 1 and the
write pointer is 5.
10000111: indicates the FIFO is half full. The read pointer is 3 and the
write pointer is 7.
00100000: indicates the FIFO has only one latched sample and is nearly
empty.
01111111: indicates the FIFO has seven latched samples and is nearly
over flowing.
Value of 1.4 multiplier applied to both I and Q channels just after the
SRRC filter.
00000: multiply by 0.0.
00001: multiply by 0.0625.
…
11111: multiply by 1.9375.
Value of 1.4 multiplier applied to both I and Q channels just after
Interpolation Filter 0.