AD9963 Analog Devices, AD9963 Datasheet - Page 46

• Manufacturer Part Number: AD9963
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9963

• Resolution (bits): 12bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 12x2-100 MHz
• Dac Bits X #dacs-clkspeed: 12x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

AD9961/AD9963
DRIVING THE CLOCK INPUT
For optimum performance, the AD9961/AD9963 clock inputs
(CLKP and CLKN) should be clocked with a low jitter, fast rise
time differential signal. This signal should be ac-coupled to the
CLKP and CLKN pins via a transformer or capacitors. The
CLKP/CLKN inputs are internally biased and require no
external bias circuitry. Figure 66 through Figure 69 show
preferred methods for clocking the AD9961/AD9963.
In applications where the receive analog input signals and the
transmit analog output signals are at low frequencies, it is
acceptable to drive the sample clock inputs with a single-ended
CMOS signal. In such applications, CLKP should be driven
directly from a CMOS gate, and the CLKN pin should be bypassed
to ground with a 0.1 μF capacitor in parallel with a 39 kΩ
resistor (see Figure 67). A series termination resistor off the
clock driver output may improve the dynamic response of the
driver.
CLK+
CLK–
CLK+
CLK–
CLK+
50Ω*
50Ω*
*50Ω RESISTORS ARE OPTIONAL.
*50Ω RESISTORS ARE OPTIONAL.
50Ω
Figure 67. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
0.1µF
0.1µF
0.1µF
50Ω*
0.1µF
0.1µF
50Ω*
Figure 66. Differential LVDS Sample Clock
Figure 68. Differential PECL Sample Clock
CLK
CLK
CLK
CLK
PECL DRIVER
LVDS DRIVER
CLK
CLK
CMOS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
240Ω
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
OPTIONAL
240Ω
100Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
39kΩ
CLK_P
CLK_N
CLK_P
CLK_N
CLK_P
CLK_N
AD9963
AD9963
AD9963
ADC
ADC
ADC
Rev. 0 | Page 46 of 60
Note that the 39 kΩ resistor shown in the CMOS clock driver
example shifts the CLK_N input to about 0.9 V. This is optimal
when the CMOS driver is supplied from a 1.8 V supply.
A 2.5 V CMOS driver may also be used. In this case, the
minimum CLK33V supply voltage should be 2.5 V. The 39 kΩ
resistor should be removed in this case. Connecting CLKN to
ground with just a 0.1 µF capacitor results in the CLKN voltage
being biased to about 1.2 V.
Clock Duty Cycle Considerations
The duty cycle of the input clock should be maintained between
45% and 55%. Duty cycles outside of this range affects the
dynamic performance of the ADC. This is especially true at
sample rates greater than 75 MHz. It is recommended that the
duty cycle stabilizer (DCS) be used at clock rates above 75 MHz
to ensure the sampling clock maintains the proper duty cycle
inside the device. Below 75 MHz, the DCS should be bypassed.
The DCS is bypassed by setting Register 0x66, Bit 2 high.
CLOCK MULTIPLICATION USING THE DLL
The AD9961/AD9963 contain a recirculating DLL, as shown in
Figure 70. This circuit allows the incoming CLK signal
(REFCLK) to be multiplied by a programmable M/N factor.
This provides a means of generating a wide range of DLL output
clock (DLLCLK) frequencies. The DLLCLK signal can be used
for either the receive ADC sampling clock, the transmit DAC
sampling clock, or both. The EXTDLLCLK signal can be
programmed to appear on the TXCLK pin or TRXCLK if
desired.
REFCLK
CLK+
DLL_REF_EN
REG 0x71[4]
Figure 70. Functional Block Diagram of Clock Multiplier DLL
50Ω
0.1µF
Figure 69. Transformer Coupled Clock
DLLLOCKED
REG 0x72[7]
Mini-Circuits®
ADT1-1WT, 1:1Z
DETECTOR
1
0
PHASE
XFMR
0.1µF
REG 0x72[4:0]
REG 0x75[3]
DLL_RESB
DELAY LINE
M[4:0]
REG 0x61[5]
DLLBIASPD
CHARGE
÷M
0.1µF
0.1µF
PUMP
SELECT
LOGIC
REG 0x60[7]
DLL_EN
SCHOTTKY
HSM2812
DIODES:
MCLK
REG 0x71[3:0]
REG 0x72[6:5]
DLLDIV[1:0]
÷DLLDIV
M[3:0]
DLLFILT
÷N
PIN 54
CLK_P
CLK_N
AD9963
ADC
EXTDLLCLK
DLLCLK