AD9261

Manufacturer Part NumberAD9261
Description16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
ManufacturerAnalog Devices
AD9261 datasheet
 


Specifications of AD9261

Resolution (bits)16bit# Chan1
Sample Rate160MSPSInterfacePar
Analog Input TypeDiff-UniAin Range2 V p-p
Adc ArchitectureSigma-DeltaPkg TypeCSP
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FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 340 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz
Output data rate: 30 MSPS to 160 MSPS
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Data acquisition
Automated test equipment
Instrumentation
Medical imaging
GENERAL DESCRIPTION
The AD9261 is a single 16-bit analog-to-digital converter
(ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves 87 dBc of dynamic range over a 10 MHz
input bandwidth. The integrated features and characteristics
unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The AD9261 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate from 30 MSPS to 160 MSPS,
enabling a more efficient and direct interface.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16-Bit, 10 MHz Bandwidth, 30 MSPS to
160 MSPS Continuous Time Sigma-Delta ADC
VIN+
MODULATOR
VIN–
VREF
CFILT
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic.
The AD9261 operates on a 1.8 V analog supply and a 1.8 V
to 3.3 V digital supply, consuming 340 mW. The AD9261 is
available in a 48-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2.
Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3.
An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4.
An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5.
This part operates from a single 1.8 V analog power supply
and 1.8 V to 3.3 V output supply.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9261
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
SAMPLE
Σ-Δ
LOW-PASS
CMOS
RATE
DECIMATION
BUFFER
CONVERTER
FILTER
PHASE
LOCKED
AD9261
LOOP
SERIAL
INTERFACE
AGND
SDIO SCLK CSB
DGND
Figure 1.
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
OR
D15
D0
PLL_
LOCKED
CLK+
CLK–
DCO

AD9261 Summary of contents

  • Page 1

    ... The digital output data is presented in offset binary, Gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper timing with the receiving logic. The AD9261 operates on a 1.8 V analog supply and a 1 3.3 V digital supply, consuming 340 mW. The AD9261 is available in a 48-lead LFCSP and is specified over the industrial temperature range (− ...

  • Page 2

    ... AD9261 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Digital Decimation Filtering Characteristics ............................ 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 4/10— ...

  • Page 3

    ... Full 1.7 1.8 Full 1.7 1.8 Full 74 Full 57 Full 8.0 Full 100 Full 5.5 Full 10 Full 340 Full 425 Full 20 Full 7 Full 3 Rev Page AD9261 1 = −2.0 dBFS, Max Unit Bits 10 MHz ±0.15 % FSR ±3.0 % FSR LSB ppm/°C ppm/°C 510 mV V p-p diff 1.9 V kΩ 1.9 V 1.9 V 1.9 V 3.6 V ...

  • Page 4

    ... See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Noise figure with respect to 50 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. DIGITAL DECIMATION FILTERING CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. ...

  • Page 5

    ... Full Full Full Full Full Full Full Full Full Full Full Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full Rev Page AD9261 Min Typ Max CMOS/LVPECL 0.4 0.8 2 0.3 0.450 0.5 −60 +60 −60 + 1.2 DRVDD + 0.3 0 0.8 −50 −75 −10 + ...

  • Page 6

    ... AD9261 SWITCHING SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 5. 1 Parameter CLOCK INPUT (USING CLOCK MULTIPLIER) Conversion Rate CLK± Period CLK± Duty Cycle ...

  • Page 7

    ... V to +3.9 V −0 +3.9 V −0 +2.5 V −0 +2.0 V −65°C to +125°C −40°C to +85°C 300°C 150°C Rev Page θ θ 27.7 11.8 and θ are specified for a 4-layer board in still air AD9261 θ Unit JC 1.1 °C ...

  • Page 8

    ... VIN+ 44 VIN– 47 CGND 48 CLK+ 49 EPAD CLK– 1 PIN 1 CVDD 2 INDICATOR PDWN 3 DVDD 4 DGND 5 AD9261 DRVDD 6 7 TOP VIEW (Not to Scale) DCO Figure 3. Pin Configuration Description Clock Input (−). Clock Supply (1.8 V). External Power-Down Pin. Digital Supply (1.8 V). ...

  • Page 9

    ... MHz, and BW = 2.5 MHz IN1 IN2 0 BANDWIDTH: 5MHz DATA RATE: 40MSPS – 2.1MHz AT –8dBFS IN1 f : 2.4MHz AT –8dBFS IN2 –40 SFDR: 91.9dBc –60 –80 –100 –120 –140 –160 FREQUENCY (MHz) = 2.1 MHz 2.4 MHz and MHz IN1 IN2 AD9261 ...

  • Page 10

    ... AD9261 All power supplies set to 1.8 V, 640 MHz sample rate p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, 10 MHz bandwidth, output data rate 40 MSPS BANDWIDTH: 10MHz DATA RATE: 40MSPS –20 f SNR: 83.2dB –40 SFDR: 92.6dBc –60 –80 –100 – ...

  • Page 11

    ... FREQUENCY (MHz) Figure 17. SNR/SFDR vs. Input Frequency 1.9V SFDR 1.8V 1.7V SNR –60 –40 – TEMPERATURE (°C) Figure 18. SFDR/SNR vs. Temperature with f IN 1.700 1.725 1.750 1.775 1.800 1.825 1.850 COMMON-MODE VOLTAGE (V) AD9261 1.9V 1.8V 1.7V 80 100 = 2.4 MHz 1.875 1.900 = 2.4 MHz IN ...

  • Page 12

    ... AD9261 84 83 2.4MHz 82 8.4MHz PLL DIVIDE RATIO Figure 20. Single-Tone SNR vs. PLL Divide Ratio Rev Page 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 OUTPUT CODE Figure 21 ...

  • Page 13

    ... Figure 25. Equivalent SCLK Input Circuit CLK– Rev Page AVDD 26kΩ 1kΩ CSB Figure 26. Equivalent CSB Input Circuit DRVDD DRGND Figure 27. Equivalent Digital Output Circuit 2.85kΩ 8.5kΩ 10kΩ 0.5V 3.5kΩ 10µF TO CURRENT GENERATOR Figure 28. Equivalent VREF Circuit AD9261 ...

  • Page 14

    ... SRC ANALOG INPUT CONSIDERATIONS The continuous time modulator removes the need for an anti- alias filter at the input to the AD9261. A discrete time converter aliases signals around the sample clock frequency and its multiples to the band of interest (see Figure 34). Therefore, an external antialias filter is needed to reject these signals. ...

  • Page 15

    ... Input Common Mode The analog inputs of the AD9261 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device such that V = AVDD is recommended for CM optimum performance. The analog inputs are 500 Ω resistors, and the internal reference loop aims to develop 0.5 V across each input resistor (see Figure 36) ...

  • Page 16

    ... CLOCK INPUT If a differential clock is not available, the AD9261 can be driven by a single-ended signal into the CLK+ terminal with the CLK− terminal ac-coupled to ground. Figure 43 shows the circuit configuration. ...

  • Page 17

    ... Internal PLL Clock Distribution The alternative clocking option available on the AD9261 is to apply a low frequency reference clock and use the on-chip clock multip- lier to generate the high frequency f MOD architecture is shown in Figure 45. CLK+/CLK– PHASE LOOP DETECTOR FILTER DIVIDER ÷N ...

  • Page 18

    ... During sleep mode, all internal circuits are powered down, putting the device into its lowest power mode, and the CMOS outputs are disabled. If the serial port interface is not available, the AD9261 can be configured in power-down mode by connecting Pin 3 (PDWN) to AVDD. Rev Page ...

  • Page 19

    ... C29, C33 −592 C30, C32 353 C31 DEC4 LPF/EQZ FIR INT4 10MHz 16 5MHz 5 2 SINC 4 8 DATA 2.5MHz OUTPUT NCO AD9261 Coefficient 1121 0 −2796 0 10,184 16,384 Coefficient 694 −744 −677 1271 450 −1909 103 2612 −1147 −3326 3022 4051 −6870 −5305 ...

  • Page 20

    ... OUT Table 18 shows the available K conversion factors. OUT If the main clocking source of the AD9261 is provided by the PLL important that once the PLL has been programmed and locked, to initiate an SRC reset before programming the desired K factor. This is done by first writing 0x101[5: ...

  • Page 21

    ... Figure 49. 2.5 MHz Signal Bandwidth, 160 MSPS DIGITAL OUTPUTS Digital Output Format The AD9261 offers a variety of digital output formats for ease of system integration. The digital output consists of 16 data bits and an output clock signal (DCO) for data latching. The data bits can be configured for offset binary, twos complement, or Gray code by writing to Register 0x14[1:0] ...

  • Page 22

    ... AD9261 Table 19. OR Threshold Levels 0x111[5:0] Threshold (dBFS) 1 −36.12 2 −30.10 3 −26.58 4 −24.08 5 −22.14 6 −20.56 7 −19.22 8 −18.06 9 −17.04 A −16.12 B −15.29 C −14.54 D −13.84 E −13.20 F −12.60 10 −12.04 11 −11.51 12 −11.02 13 −10.56 14 −10.10 15 −9.68 Table 20. OR Conditions OR Conditions AUTORST OR_IND Normal, Reset Off 0 0 Digital Threshold, ...

  • Page 23

    ... SERIAL PORT INTERFACE (SPI) The AD9261 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

  • Page 24

    ... The pins described in Table 21 comprise the physical interface between the programming device of the user and the serial port of the AD9261. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 25

    ... MSB first format 1: serial interface uses LSB first format SOFTRESET 0 1: default all serial registers except 0x00, 0x09, and 0x0A CHIPID 0x26 0x26: AD9261 CHILDID 0 0x00: 10 MHz bandwidth PWRDWN 0 0x0: normal operation 0x1: power-down (local) 0x2: standby (everything except reference circuits) ...

  • Page 26

    ... AD9261 Register Address Bit(s) Output Adjust 0x15 [3:2] [1:0] Output Clock 0x16 7 Reference 0x18 6 Output Data 0x101 [5:0] Overrange 0x111 7 6 [5:0] Mnemonic Default Description DRVSTR33 0 Typical output sink current to DGND 120 mA DRVSTR18 2 Typical output sink current to DGND ...

  • Page 27

    ... Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Rev Page 0.30 0.23 0.18 PIN 1 INDICATOR 48 1 EXPOSED 5.25 PAD 5.10 SQ (BOTTOM VIEW) 4. 0.25 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-48-1 CP-48-1 AD9261 ...

  • Page 28

    ... AD9261 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07803-0-4/10(0) Rev Page ...