AD9261 Analog Devices, AD9261 Datasheet - Page 15

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AD9261

Manufacturer Part Number
AD9261
Description
16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
Manufacturer
Analog Devices
Datasheet

Specifications of AD9261

Resolution (bits)
16bit
# Chan
1
Sample Rate
160MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
2 V p-p
Adc Architecture
Sigma-Delta
Pkg Type
CSP
Input Common Mode
The analog inputs of the AD9261 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device such that V
optimum performance. The analog inputs are 500 Ω resistors,
and the internal reference loop aims to develop 0.5 V across
each input resistor (see Figure 36). With 0 V differential input,
the driver sources 1 mA into each analog input.
Differential Input Configurations
The AD9261 can also be configured for differential inputs. The
ADA4937-1 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the ADA4937-1 is easily set by connecting AVDD to
the V
linearity of the ADA4937-1 needs important consideration because
the system performance may be limited by the ADA4937-1.
For frequencies offset from dc, where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 38. The center
tap of the secondary winding of the transformer is connected to
AVDD to bias the analog input.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a couple of megahertz (MHz), and excessive signal power
can cause core saturation, which leads to distortion.
V
V
CM
IN
p-p = 2V
V
= AVDD
50Ω
Figure 37. Differential Input Configuration Using the ADA4937-1
OCM
SOURCE
S
SIGNAL
49.9Ω
0.1µF
pin of the ADA4937-1 (see Figure 37). The noise and
VIN+
VIN–
2V p-p
500Ω
500Ω
R
60.4Ω
Figure 36. Input Common Mode
T
60.4Ω
AVDD – 0.5V
200Ω
V
0.1µF
OCM
DAC
2
9
3
0.1µF
ADA4937-1
CM
15
+5V
–5V
8
= AVDD is recommended for
200Ω
200Ω
10
11
VIN–
TO LOOP FILTER
FROM QUANTIZER
VIN+
AD9261
STAGE 2
+1.8V
AVDD
0.1µF
Rev. 0 | Page 15 of 28
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9261. The reference voltage should be decoupled to minimize
the noise bandwidth using a 10 μF capacitor. The reference is
used to generate a bias current into a matched resistor such that,
when used to bias the current in the feedback DAC, a voltage
of AVDD − 0.5 V is developed at the internal side of the input
resistors (see Figure 39). The current bias circuit should also be
decoupled on the CFILT pin with a 10 μF capacitor. For this
reason, the VREF voltage should always be 0.5 V.
Internal Reference Connection
To minimize thermal noise, the internal reference on the AD9261
is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor,
which, when externally decoupled with a 10 μF capacitor, limits
the noise (see Figure 40). The unbuffered reference should not
be used to drive any external circuitry. The internal reference is
used by default.
0.5V
10µF
VREF
10kΩ
V
10µF
50Ω
10µF
SOURCE
S
Figure 38. Differential Transformer Configuration
SIGNAL
Figure 40. Internal Reference Configuration
V
V
CM
IN
TO CURRENT
GENERATOR
CFILT
Figure 39. Voltage Reference Loop
p-p = 2V
AVDD – 0.5V
= AVDD
2V p-p
10kΩ
REF
R
50Ω
T
VIN+
VIN–
0.5V
1:1
AVDD
500Ω
500Ω
500Ω
0.1µF
2.85kΩ
VIN+
VIN–
AVDD – 0.5V
3.5kΩ
AD9261
8.5kΩ
AVDD
AD9261
TO LOOP
STAGE 2
FILTER

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