AD9261 Analog Devices, AD9261 Datasheet - Page 16

• Manufacturer Part Number: AD9261
• Description: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9261

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9261
External Reference Operation
If an external reference is desired, the internal reference can be
disabled by setting Register 0x18[6] high. Figure 41 shows an
application using the
CLOCK INPUT CONSIDERATIONS
The AD9261 offers two modes of sourcing the ADC sample
clock (CLK+ and CLK−). The first mode uses an on-chip clock
multiplier that accepts a reference clock operating at the lower
input frequency. The on-chip phase-locked loop (PLL) then
multiplies the reference clock up to a higher frequency, which is
then used to generate all the internal clocks required by the ADC
The clock multiplier provides a high quality clock that meets
the performance requirements of most applications. Using the
on-chip clock multiplier removes the burden of generating and
distributing the high speed clock.
The second mode bypasses the clock multiplier circuitry and
allows the clock to be directly sourced. This mode enables the
user to source a very high quality clock directly to the Σ-Δ
modulator. Sourcing the ADC clock directly may be necessary
in demanding applications that require the lowest possible ADC
output noise. Refer to Figure 20, which shows the degradation
in SNR performance for the various PLL settings.
In either case, when using the on-chip clock multiplier or
sourcing the high speed clock directly, it is necessary that the
clock source have low jitter to maximize the ADC noise
performance. High speed, high resolution ADCs are sensitive to
the quality of the clock input. As jitter increases, the SNR
performance of the AD9261 degrades from that specified in
Table 2. The jitter inherent to the part due to the PLL root sum
squares with any external clock jitter, thereby degrading
performance. To prevent jitter from dominating the performance
of the AD9261, the input clock source should be no greater than
1 ps rms of jitter.
The CLK± inputs are self-biased to 450 mV (see Figure 23); if
dc-coupled, it is important to maintain the specified 450 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p single-ended about the 450 mV
common-mode voltage. The recommended clock inputs are
CMOS or LVPECL.
The specified clock rate of the Σ-Δ modulator, f
The clock rate possesses a direct relationship with the available
input bandwidth of the ADC.
Bandwidth = f
AVDD
0.1µF
Figure 41. External Reference Configuration
MOD
ADR130B
ADR130B
÷ 64
as a stable external reference.
10µF
0.5V
10kΩ
TO CURRENT
GENERATOR
MOD
, is 640 MHz.
Rev. 0 | Page 16 of 28
In either case, using the on-chip clock multiplier to generate the
Σ-Δ modulator clock rate or directly sourcing the clock, any
deviation from 640 MHz results in a change in input bandwidth.
The input range of the clock is limited to 640 MHz ± 5%.
Direct Clocking
The default configuration of the AD9261 is for direct clocking
where the PLL is bypassed. Figure 42 shows one preferred method
for clocking the AD9261. A low jitter clock source is converted
from a single-ended signal to a differential signal using an RF
transformer. The back-to-back Schottky diodes across the
secondary side of the transformer limits clock excursions into the
AD9261 to approximately 0.8 V p-p differential. This helps
prevent the large voltage swings of the clock from feeding
through to other portions of the AD9261 while preserving the
fast rise and fall times of the signal, which are critical to
achieving low jitter.
If a differential clock is not available, the AD9261 can be driven
by a single-ended signal into the CLK+ terminal with the CLK−
terminal ac-coupled to ground. Figure 43 shows the circuit
configuration.
Another option is to ac couple a differential LVPECL signal to
the sample clock input pins, as shown in Figure 44. The AD951x
family of clock drivers is recommended because it offers excellent
jitter performance.
CLOCK
CLOCK
1
INPUT
INPUT
50Ω RESISTORS ARE OPTIONAL.
CLOCK
INPUT
CLOCK
INPUT
50Ω
Figure 42. Transformer-Coupled Differential Clock
1
50Ω
0.1µF
Figure 44. Differential LVPECL Sample Clock
50Ω
0.1µF
0.1µF
1
50Ω
Figure 43. Single-Ended Clock
MINI-CIRCUITS
TC1-1-13M+, 1:1
CLK
CLK
LVPECL
AD951x
DRIVER
0.1µF
XFMR
0.1µF
240Ω
0.1µF
0.1µF
0.1µF
®
SCHOTTKY
HSM2812
DIODES:
SCHOTTKY
HSM2812
DIODES:
240Ω
100Ω
CLK+
CLK–
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9261
ADC
AD9261
AD9261
ADC
ADC