AD9261 Analog Devices, AD9261 Datasheet - Page 17

• Manufacturer Part Number: AD9261
• Description: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9261

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

Internal PLL Clock Distribution
The alternative clocking option available on the AD9261 is to apply
a low frequency reference clock and use the on-chip clock multip-
lier to generate the high frequency f
architecture is shown in Figure 45.
The clock multiplication circuit operates such that the VCO
outputs a frequency, f
multiplied by N
where N is the PLL multiplication (PLLMULT) factor.
The Σ-Δ modulator clock frequency, f
The reference clock, CLK±, is limited to 30 MHz to 160 MHz
when configured to use the on-chip clock multiplier. Given the
input range of the reference clock and the available multiplication
factors, the f
desired f
Before the PLL enable (PLLENABLE) register bit is set, the PLL
multiplication factor should be programmed into Register
0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and
reports a locked state in Register 0x0A[7]. If the PLL multiplica-
tion factor is changed, the PLL enable bit should be reset and set
again. Some common clock multiplication factors are shown in
Table 11.
The recommended sequence for enabling and programming the
on-chip clock multiplier is summarized in Table 9.
Table 9. Sequence for Enabling and Programming the PLL
Step
1
2
3
4
5
6
CLK+/CLK–
f
f
MOD
VCO
MOD
= (CLK±) × (N)
= f
VCO
Procedure
Apply a reference clock to the CLK± pins.
Program the PLL multiplication factor in
Register 0x0A[5:0]. See Table 10.
Enable the PLL; Register 0x09 = 04 (decimal).
Enable the PLL autoband select.
Initiate an SRC reset; Register 0x101[5:0] = 0.
Set SRC to the desired value via Register 0x101[5:0].
VCO
rate of 640 MHz with a 50% duty cycle.
÷ 2
is approximately 1280 MHz. This results in the
Figure 45. Internal Clock Architecture
DETECTOR
PHASE
VCO
, equal to the reference clock input
PLL MULT
0x0A[5:0]
DIVIDER
÷N
FILTER
LOOP
MOD
MOD
rate. The internal clock
PLL
, is equal to
÷2
PLLENABLE
1.28GHz
0x09[2]
VCO
MODULATOR
640MSPS
CLOCK
Rev. 0 | Page 17 of 28
Table 10. Internal PLL Multiplication Factors
0x0A[5:0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
External PLL Control
At power-up, the serial interface is disabled until the first serial
port access. If the serial interface is disabled, the PLLMULTx
pins control the PLL multiplication factor. The five PLLMULTx
pins (Pin 32 to Pin 36) offer all the available multiplication
factors. If all PLLMULTx pins are tied high, the PLL is disabled
and the AD9261 assumes the high frequency modulator clock
rate that is applied to the CLK± pins. Table 12 shows the relation-
ship between PLLMULTx pins and the PLL multiplication factor.
PLLMULT (N)
8
8
8
8
8
8
8
8
9
10
10
12
12
14
15
16
17
18
18
20
21
21
21
24
25
25
25
28
28
30
30
32
0x0A[5:0]
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PLLMULT (N)
32
34
34
34
34
34
34
34
34
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
AD9261