AD9261 Analog Devices, AD9261 Datasheet - Page 20

• Manufacturer Part Number: AD9261
• Description: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9261

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9261
Sample Rate Converter
The sample rate converter (SRC) allows the flexibility of a user-
defined output sample rate, enabling a more efficient and direct
interface to the digital receiver blocks.
The sample rate converter performs an interpolation and
resampling procedure to provide an output data rate of
20 MSPS to 168 MSPS. Table 16 and Table 17 detail the coeffi-
cients for the INT1 and INT2 filters. The sinc filters are a
standard implementation.
Table 16. INT1 Filter Coefficients
Coefficient
Number
C0, C26
C1, C25
C2, C24
C3, C23
C4, C22
C5, C21
C6, C20
Table 17. INT2 Filter Coefficients
Coefficient
Number
C0, C14
C1, C13
C2, C12
C3, C11
The relationship between the output sample rate and the Σ-Δ
modulator clock rate is expressed as follows:
Table 18 shows the available K
If the main clocking source of the AD9261 is provided by the
PLL, it is important that once the PLL has been programmed
and locked, to initiate an SRC reset before programming the
desired K
and then rewriting to the same register with the appropriate
K
then later regains it, an SRC reset should be initiated.
OUT
f
value. In addition, if the AD9261 loses its clock source and
OUT
= f
OUT
MOD
factor. This is done by first writing 0x101[5:0] = 0
÷ K
Coefficient
15
0
−97
0
361
0
−1017
Coefficient
−27
0
227
0
OUT
OUT
conversion factors.
Coefficient
Number
C7, C19
C8, C18
C9, C17
C10, C16
C11, C15
C12, C14
C13
Coefficient
Number
C4, C10
C5, C9
C6, C8
C7
Coefficient
0
2450
0
−5761
0
20433
32768
Coefficient
−1032
0
4928
8192
Rev. 0 | Page 20 of 28
Table 18. SRC Conversion Factors
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Cascaded Filter Responses
The cascaded filter responses for the three signal bandwidth
settings are for a 160 MSPS output data rate, as shown in Figure 47,
Figure 48, and Figure 49.
0x101[5:0]
–100
–120
–140
–160
–20
–40
–60
–80
0
0
Figure 47. 10 MHz Signal Bandwidth, 160 MSPS
SRC reset
4
4
4
4
4
4
4
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
10
K
OUT
20
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
0x101[5:0]
FREQUENCY (MHz)
30
–0.04
–0.08
0.08
0.04
0
0
40
2
FREQUENCY (MHz)
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
16.5
17
17.5
18
18.5
19
19.5
20
20.5
21
21.5
K
50
4
OUT
60
6
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0x101[5:0]
8
70
10
80
22
22.5
23
23.5
24
24.5
25
25.5
26
26.5
27
27.5
28
28.5
29
29.5
30
30.5
31
31.5
K
OUT