AD9262

Manufacturer Part NumberAD9262
Description16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC
ManufacturerAnalog Devices
AD9262 datasheet
 


Specifications of AD9262

Resolution (bits)16bit# Chan2
Sample Rate160MSPSInterfacePar
Analog Input TypeDiff-UniAin Range2 V p-p
Adc ArchitectureSigma-DeltaPkg TypeCSP
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FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: −87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 600 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz real
5 MHz/10 MHz/20 MHz complex
Output data rate: 30 MSPS to 160 MSPS
Integrated dc and quadrature correction
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Baseband quadrature receivers: CDMA2000, W-CDMA,
multicarrier GSM/EDGE, 802.16x, and LTE
Quadrature sampling instrumentation
Medical equipment
Radio detection and ranging (RADAR)
GENERAL DESCRIPTION
The AD9262 is a dual channel, 16-bit analog-to-digital conver-
ter (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves −87 dBc of dynamic range over a
10 MHz input bandwidth. The integrated features and characteris-
tics unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The AD9262 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate between 30 MSPS and 160 MSPS,
enabling a more efficient and direct interface.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to
160 MSPS Dual Continuous Time Sigma-Delta ADC
VIN+A
MODULATOR
VIN–A
VREF
CFILT
VIN–B
MODULATOR
VIN+B
CLK+
CLK–
The AD9262 incorporates an integrated dc correction and
quadrature estimation block that corrects for gain and phase
mismatch between the two channels. This functional block
proves invaluable in complex signal processing applications
such as direct conversion receivers.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic. The
AD9262 has the added feature of interleaving Channel A and
Channel B data onto one 16-bit bus, simplifying on-board routing.
The ADC is available in three different bandwidth options of
2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog
supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW.
The AD9262 is available in a 64-lead LFCSP and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2.
Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3.
An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4.
An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5.
Integrated dc correction and quadrature error correction.
6.
Operates from a single 1.8 V analog power supply and
1.8 V to 3.3 V output supply.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9262
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
SAMPLE
LOW-PASS
CT Σ-Δ
DC
CMOS
RATE
DECIMATION
CORRECT
BUFFER
CONVERTER
FILTER
QUADRATURE
ERROR
ESTIMATE
AD9262
LOW-PASS
SAMPLE
CT Σ-Δ
DC
CMOS
DECIMATION
RATE
CORRECT
BUFFER
FILTER
CONVERTER
PHASE-
SERIAL
LOCKED
INTERFACE
LOOP
AGND
SDIO SCLK
CSB
Figure 1
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ORA
D15A
D0A
GAIN
ADJ
PHASE
ADJ
DCO
D15B
D0B
ORB
DGND

AD9262 Summary of contents

  • Page 1

    ... The ADC is available in three different bandwidth options of 2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog supply and a 1 3.3 V digital supply, consuming 600 mW. The AD9262 is available in a 64-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. Continuous time Σ ...

  • Page 2

    ... ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 10 AD9262BCPZ ............................................................................. 10 AD9262BCPZ-5 .......................................................................... 11 REVISION HISTORY 2/10—Rev Rev. A Changes to Figure 61 ...................................................................... 28 1/10—Revision 0: Initial Version   AD9262BCPZ-10 ....................................................................... 12   Equivalent Circuits ......................................................................... 15   Theory of Operation ...................................................................... 16   Analog Input Considerations ................................................... 16   Clock Input Considerations ...................................................... 18   Power Dissipation and Standby Mode .................................... 20   ...

  • Page 3

    ... Rev Page AD9262 1 = −2.0 dBFS, AD9262BCPZ-10 Max Min Typ Max Unit 16 Bits 10 MHz Guaranteed ±0.2 ±0.025 ±0.2 % FSR ±3.0 ±0.7 ±3.0 % FSR ±1.5 LSB ±0.2 ±0.035 ±0.2 % FSR ± ...

  • Page 4

    ... Data guaranteed over the full temperature range for the AD9262BCPZ-10 only. 5 Noise figure with respect to 50 Ω. AD9262 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. 6 Crosstalk measured with an input signal on both channels at different frequencies and the leakage of one on to the other. ...

  • Page 5

    ... See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. AD9262BCPZ-5 Max Min Typ 3.75 5 <0 6.5 MHz − − >85 Rev Page AD9262 AD9262BCPZ-10 Max Min Typ Max 6 <0.1 13 MHz f /2 − S >85 Unit MHz dB ...

  • Page 6

    ... AD9262 DIGITAL SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 4. 1 Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Range ...

  • Page 7

    ... See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data skew is measured from DCO 50% transition to data (D0x to D15x) 50% transition, with 5 pF load. 3 Typical measured value for the AD9262BCPZ-10. For the AD9262BCPZ-5 and the AD9262BCPZ, typical values double and quadruple the number of cycles, respectively. 4 Cycles refers to modulator clock cycles. 5 Wake-up time is dependent on the value of the decoupling capacitor, value shown with 10uF capacitor on VREF and CFILT ...

  • Page 8

    ... AD9262 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DVDD to DGND DRVDD to DGND AGND to DGND AVDD to DRVDD CVDD to CGND CGND to DGND D0A to D15A to DGND D0B to D15B to DGND DCO to DGND ORA, ORB to DGND SDIO to DGND CSB to AGND SCLK to AGND VIN+A/VIN−A, VIN+B/VIN−B to AGND CLK+, CLK− ...

  • Page 9

    ... Noise Limiting Filter Capacitor. Channel B Analog Input (+). Channel B Analog Input (−). Clock Ground. Clock Input (+). Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed pad must be soldered to ground. Rev Page AD9262 48 SCLK 47 SDIO 46 ORA 45 D15A ...

  • Page 10

    ... FREQUENCY (MHz) Figure 6. AD9262BCPZ Single-Tone FFT with f : 600kHz AT –2dBFS Figure 7. AD9262BCPZ Single-Tone SNR and SFDR vs. Input Amplitude = 600 kHz IN BANDWIDTH: 2.5MHz DATA RATE: 40MSPS f : 1.2MHz AT –2dBFS IN SNR: 87.7dB SFDR: 87.1dBc 1.2 MHz IN BANDWIDTH: 2.5MHz ...

  • Page 11

    ... Figure 12. AD9262BCPZ-5 Single-Tone FFT with f BANDWIDTH: 5MHz DATA RATE: 40MSPS f : 1.2MHz AT –2dBFS IN SNR: 85.3dB SFDR: 87.1dBc 1.2 MHz Figure 13. AD9262BCPZ-5 Single-Tone SNR and SFDR vs. Input Amplitude with IN : 2.4MHz AT –2dBFS 2.4 MHz Figure 14. AD9262BCPZ-5 Two-Tone FFT with 4.2MHz AT –2dBFS IN ...

  • Page 12

    ... FREQUENCY (MHz) Figure 18. AD9262BCPZ-10 Single-Tone FFT with f : 2.4MHz AT –2dBFS 2.4 MHz Figure 19. AD9262BCPZ-10 Two-Tone FFT with 4.2MHz AT –2dBFS 4.2 MHz Figure 20. AD9262BCPZ-10 Two-Tone FFT with f IN BANDWIDTH: 10MHz DATA RATE: 40MSPS f : 8.4MHz AT –2dBFS IN SNR: 82.6dB SFDR: 104 ...

  • Page 13

    ... SNR (dB 100 OUTPUT DATA RATE (MSPS) Figure 24. AD9262BCPZ-10 SNR/SFDR vs. Output Data Rate with f SNR (dB) –30 –20 –10 –30 –20 –10 Figure 26. AD9262BCPZ-10 SFDR/SNR vs. Temperature with f 120 140 160 180 = 2.4 MHz Figure 27. AD9262BCPZ-10 SNR vs. Input Common-Mode Voltage IN Rev ...

  • Page 14

    ... AD9262 83 2.4MHz 82.5 IN 82.0 f 81.5 = 8.4MHz IN 81.0 80.5 80.0 79.5 79.0 78.5 78.0 1.0 4.5 6.0 7.5 8.5 10.0 4.0 5.0 7.0 8.0 9.0 10.5 PLL DIVIDE RATIO Figure 28. AD9262BCPZ-10 Single-Tone SNR vs. PLL Divide Ratio 12.0 14.0 16.0 21.0 12.5 15.0 17.0 Rev Page 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 OUTPUT CODE Figure 29. AD9262BCPZ-10 INL ...

  • Page 15

    ... Figure 33. Equivalent SCLK Input Circuit CLK– Rev Page AVDD 26kΩ 1kΩ CSB Figure 34. Equivalent CSB Input Circuit DRVDD DGND Figure 35. Equivalent Digital Output Circuit 2.85kΩ 8.5kΩ 10kΩ 0.5V 10µF 3.5kΩ TO CURRENT GENERATOR Figure 36. Equivalent VREF Circuit AD9262 ...

  • Page 16

    ... SRC ANALOG INPUT CONSIDERATIONS The continuous time modulator removes the need for an anti- alias filter at the input to the AD9262. A discrete time converter aliases signals around the sample clock frequency and its multiples to the band of interest (see Figure 42). Therefore, an external antialias filter is needed to reject these signals. ...

  • Page 17

    ... Input Common Mode The analog inputs of the AD9262 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device such that V = AVDD is recommended for CM optimum performance. The analog inputs are 500 Ω resistors, and the internal reference loop aims to develop 0.5 V across each input resistor (see Figure 44) ...

  • Page 18

    ... CLOCK INPUT If a differential clock is not available, the AD9262 can be driven by a single-ended signal into the CLK+ terminal with the CLK− terminal ac-coupled to ground. Figure 51 shows the circuit configuration. ...

  • Page 19

    ... Internal PLL Clock Distribution The alternative clocking option available on the AD9262 is to apply a low frequency reference clock and use the on-chip clock multip- lier to generate the high frequency f MOD architecture is shown in Figure 53. CLK+/CLK– PHASE LOOP DETECTOR FILTER DIVIDER PLL MULT 0x0A[5:0] Figure 53 ...

  • Page 20

    ... From the calculation, the aperture jitter of the input clock must be no greater than achieve optimal SNR performance. POWER DISSIPATION AND STANDBY MODE The AD9262 power consumption can be further reduced MOD configuring the chip in channel power-down, standby, or sleep ...

  • Page 21

    ... C29, C33 −592 C30, C32 353 C31 DEC4 LPF/EQZ FIR INT4 10MHz 16 5MHz 5 2 SINC 4 8 DATA 2.5MHz OUTPUT NCO AD9262 Coefficient 1121 0 −2796 0 10,184 16,384 Coefficient 694 −744 −677 1271 450 −1909 103 2612 −1147 −3326 3022 4051 −6870 −5305 ...

  • Page 22

    ... SRC reset before programming the desired K factor. This is done by first writing 0x101[5: and OUT then rewriting to the same register with the appropriate K value. In addition, if the AD9262 loses its clock source and then later regains it, an SRC reset should be initiated. Table 18. SRC Conversion Factors 0x101[5:0] K ...

  • Page 23

    ... In a zero-IF receiver, this dc energy can cause problems because it appears in band of a desired channel. As part of the AD9262 QEC function, the dc offset is suppressed by applying a low frequency notch filter to form a null around dc. The 3 dB bandwidth of this notch filter ...

  • Page 24

    ... DIGITAL OUTPUTS Digital Output Format The AD9262 offers a variety of digital output formats for ease of system integration. The digital output on each channel consists of 16 data bits and an output clock signal (DCO) for data latching. The data bits can be configured for offset binary, twos comple- ment, or Gray code by writing to Register 0x14[1:0] ...

  • Page 25

    ... TIMING The AD9262 provides a data clock out (DCO) pin to assist in capturing the data in an external register. The data outputs are valid on the rising edge of DCO, unless changed by setting Serial Register 0x16[7] (see the Serial Port Interface (SPI) section) ...

  • Page 26

    ... AD9262 SERIAL PORT INTERFACE (SPI) The AD9262 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

  • Page 27

    ... The pins described in Table 22 comprise the physical interface between the programming device of the user and the serial port of the AD9262. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 28

    ... FREQUENCY (MHz) Figure 61. STF Figure 61 shows the gain profile of the AD9262, and this can be interpreted as the level at which the signal power should be scaled back to prevent an overload condition. This is the ulti- mate trip point and before this point is reached, the in-band noise (IBN) slowly degrades ...

  • Page 29

    ... Murata GRM188 series, 0603 In addition to matching the profile of Figure 62, group delay and channel matching are important filter design criteria. Low tolerance components are highly recommended for improved channel matching, which translates to minimal degradation in image rejection for quadrature systems. Rev Page AD9262 ...

  • Page 30

    ... MSB first format 1: serial interface uses LSB first format SOFTRESET 0 1: default all serial registers except 0x00, 0x09, and 0x0A CHIPID 0x22 0x22: AD9262 CHILDID 0 0x00: 10 MHz bandwidth 0x10: 5 MHz bandwidth 0x20: 2.5 MHz bandwidth Channel 0 0: both channels addressed simultaneously ...

  • Page 31

    ... PHASEENB 0 1: disable phase correction GAINENB 0 1: disable gain correction DCFRC 0 1: force dc correction coefficients to initial static values PHASEFRC 0 1: force phase correction coefficients to initial static values GAINFRC 0 1: force gain correction coefficients to initial static values Rev Page AD9262 ...

  • Page 32

    ... Temperature Range AD9262BCPZ-10 −40°C to +85°C AD9262BCPZ-5 −40°C to +85°C AD9262BCPZ −40°C to +85°C AD9262EBZ AD9262-5EBZ AD9262-10EBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 9.00 BSC SQ ...