AD9262 Analog Devices, AD9262 Datasheet - Page 22

• Manufacturer Part Number: AD9262
• Description: 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD9262

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 160MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9262
Sample Rate Converter
The sample rate converter (SRC) allows the flexibility of a
user-defined output sample rate, enabling a more efficient
and direct interface to the digital receiver blocks.
The sample rate converter performs an interpolation and
resampling procedure to provide an output data rate of
20 MSPS to 168 MSPS. Table 16 and Table 17 detail the
coefficients for the INT1 and INT2 filters. The sinc filters
are a standard implementation.
The relationship between the output sample rate and the Σ-Δ
modulator clock rate is expressed as follows:
Table 18 shows the available K
Table 16. INT1 Filter Coefficients
Coefficient
Number
C0, C26
C1, C25
C2, C24
C3, C23
C4, C22
C5, C21
C6, C20
Table 17. INT2 Filter Coefficients
Coefficient
Number
C0, C14
C1, C13
C2, C12
C3, C11
f
OUT
= f
MOD
÷ K
OUT
Coefficient
15
0
−97
0
361
0
−1017
Coefficient
−27
0
227
0
OUT
conversion factors.
Coefficient
Number
C7, C19
C8, C18
C9, C17
C10, C16
C11, C15
C12, C14
C13
Coefficient
Number
C4, C10
C5, C9
C6, C8
C7
Coefficient
0
2450
0
−5761
0
20,433
32,768
Coefficient
−1032
0
4928
8192
Rev. A | Page 22 of 32
If the main clocking source of the AD9262 is provided by the
PLL, it is important, once the PLL has been programmed and
locked, to initiate an SRC reset before programming the desired
K
then rewriting to the same register with the appropriate K
value. In addition, if the AD9262 loses its clock source and then
later regains it, an SRC reset should be initiated.
Table 18. SRC Conversion Factors
0x101[5:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
OUT
factor. This is done by first writing 0x101[5:0] = 0 and
K
SRC reset
4
4
4
4
4
4
4
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
OUT
0x101[5:0]
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
K
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
16.5
17
17.5
18
18.5
19
19.5
20
20.5
21
21.5
OUT
0x101[5:0]
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
OUT
K
22
22.5
23
23.5
24
24.5
25
25.5
26
26.5
27
27.5
28
28.5
29
29.5
30
30.5
31
31.5
OUT