AD9269

Manufacturer Part NumberAD9269
Description16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9269 datasheet
 

Specifications of AD9269

Resolution (bits)16bit# Chan2
Sample Rate80MSPSInterfacePar
Analog Input TypeDiff-UniAin Range2 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9269
VIN+A
VIN–A
VREF
SENSE
REF
VCM
SELECT
RBIAS
VIN–B
VIN+B
CLK+ CLK–
PRODUCT HIGHLIGHTS
1.
The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3.
An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4.
A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5.
The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the
ADC, the
AD9258
the
AD9231
12-bit ADC, the
diversity receiver, and the
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9269
GND
SDIO
SCLK
CSB
SPI
ORA
PROGRAMMING DATA
D15A
ADC
D0A
DCOA
QUADRATURE
ERROR
DRVDD
CORRECTION
ORB
D15B
ADC
D0B
DCOB
DIVIDE
DUTY CYCLE
MODE
1 TO 6
STABILIZER
CONTROLS
SYNC
DCS
PDWN DFS
OEB
Figure 1.
AD9268
16-bit
14-bit ADC, the
AD9251
14-bit ADC
AD6659
12-bit baseband
AD9204
10-bit ADC, enabling a
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.

AD9269 Summary of contents

  • Page 1

    ... VIN–B VIN+B CLK+ CLK– PRODUCT HIGHLIGHTS 1. The AD9269 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...

  • Page 2

    ... Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 13 AD9269-80 .................................................................................. 13 AD9269-65 .................................................................................. 15 AD9269-40 .................................................................................. 16 AD9269-20 .................................................................................. 17 Equivalent Circuits ......................................................................... 18 Theory of Operation ...................................................................... 19 ADC Architecture ...................................................................... 19 Analog Input Considerations .................................................... 19 Voltage Reference ....................................................................... 21 REVISION HISTORY 1/10—Revision 0: Initial Version   Clock Input Considerations ...................................................... 22   ...

  • Page 3

    ... GENERAL DESCRIPTION The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range ...

  • Page 4

    ... Rev Page AD9269-80 Max Min Typ Max 16 Guaranteed ±0.50 ±0.05 ±0.50 −2.0 −0.9/+1.4 −0.9/+1.65 −0.5/+1.1 ±6.50 ±6.50 ±3.3 ±0.55 ±0.0 ±0.65 ±0.2 ±2 1.005 0.981 0.993 1.005 2 2.8 2 6.5 0.9 1.3 0.5 1.3 7.5 1.9 1.7 1.8 1.9 3 ...

  • Page 5

    ... Standby power is measured with a dc input and the CLK+, CLK− active. AD9269-65 Typ Max Min Typ 87.7/121.7 170.7 96.9/136.3 102.0/142.3 191.2 114.4/165.7 235.6 37/37 37 1.0 1.0 Rev Page AD9269 AD9269-80 Max Min Typ Max 200 199.8 224.6 240 279 37 1.0 Unit ...

  • Page 6

    ... Full 25°C 25°C 95 25°C 90 Full 80 80 25°C 89 Full 25°C 25°C −99 25°C −100 Full −90 25°C −99 Full 25°C 25°C 90 Full −110 25°C 700 Rev Page AD9269-65 AD9269-80 Typ Max Min Typ Max 77.5 77.6 77.5 77.2 76.5 76.3 75.5 71.0 77.4 77.4 77.2 76.9 76.4 76.1 75.0 69.4 12.6 12.6 12.5 12.5 12.4 12.3 11.2 −97 −93 −93 −92 − ...

  • Page 7

    ... Full Full 1.2 Full 0 Full −10 Full 40 Full Full Full 1.2 Full 0 Full −10 Full 40 Full Full Full 3.29 Full 3.25 Full Full Full 1.79 Full 1.75 Full Full Rev Page AD9269 Typ Max CMOS/LVDS/LVPECL 0.9 3.6 AVDD + 0.2 +10 + DRVDD + 0.3 0.8 −75 + DRVDD + 0.3 0.8 +10 135 26 2 DRVDD + 0.3 0.8 +10 130 26 5 0.2 0.05 0.2 0.05 ...

  • Page 8

    ... CLK t DCO t SKEW – – – – Figure 3. CMOS Interleaved Output Timing Rev Page AD9269-65 AD9269-80 Min Typ Max Min Typ 480 15.38 12.5 7.69 6.25 1.0 1.0 0.1 0 0.1 0 ...

  • Page 9

    ... SCLK falling edge t Time required for the SDIO pin to switch from an output to an DIS_SDIO input relative to the SCLK rising edge CLK+ SYNC t t SSYNC HSYNC Figure 4. SYNC Input Timing Requirements Rev Page AD9269 Min Typ Max Unit 0. ...

  • Page 10

    ... AD9269 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND ...

  • Page 11

    ... SYNC 3 4 D1B 5 D2B 6 D3B 7 AD9269 D4B 8 TOP VIEW D5B 9 (Not to Scale) 10 D6B 11 D7B 12 D8B 13 D9B 14 D10B 15 D11B 16 Figure 5. Pin Configuration Rev Page AD9269 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS 44 SDIO/DCS 43 ORA 42 D15A (MSB) 41 D14A 40 D13A 39 D12A 38 D11A 37 DRVDD 36 D10A 35 D9A 34 D8A ...

  • Page 12

    ... AD9269 Pin No. Mnemonic Description 49, 50, 53, 54, AVDD 1.8 V Analog Supply Pins. 59, 60, 63, 64 51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs. 58 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. ...

  • Page 13

    ... SNR = 70dB (71dBFS) SFDR = 79.7dBc –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 10. AD9269-80 Single-Tone FFT with f 10 –10 SFDR (dBc) –30 IMD3 (dBc) –50 –70 SFDR (dBFS) –90 –110 IMD3 (dBFS) –130 –95 –85 –75 – ...

  • Page 14

    ... SNR (dBFS SAMPLE RATE (MSPS) Figure 13. AD9269-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 0 16,384 32,768 OUTPUT CODE Figure 14. DNL Error with f IN 150 200 Figure 15. AD9269-80 SNR/SFDR vs. Input Amplitude (AIN) with f ...

  • Page 15

    ... FREQUENCY (MHz) Figure 20. AD9269-65 Single-Tone FFT with f 120 100 –65 –60 = 9.7 MHz Figure 21. AD9269-65 SNR/SFDR vs. Input Amplitude (AIN) with f IN 100 MHz Figure 22. AD9269-65 SNR/SFDR vs. Input Frequency (AIN) with ...

  • Page 16

    ... FREQUENCY (MHz) Figure 24. AD9269-40 Single-Tone FFT with f 120 100 Figure 25. AD9269-40 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz 30.6 MHz IN Rev Page SFDRFS 80 SNRFS SFDR 60 SNR –65 –60 –50 – ...

  • Page 17

    ... FREQUENCY (MHz) Figure 27. AD9269-20 Single-Tone FFT with f 120 100 Figure 28. AD9269-20 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz 30.6 MHz IN Rev Page SFDRFS SNRFS SFDR (dBc) SNR (dBc) 0 –90 –80 –70 –60 –50 – ...

  • Page 18

    ... AD9269 EQUIVALENT CIRCUITS AVDD VIN±x Figure 29. Equivalent Analog Input Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ Figure 30. Equivalent SDIO/DCS Input Circuit DRVDD 350Ω SCLK/DFS, SYNC, OEB, AND PDWN 30kΩ Figure 31. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit ...

  • Page 19

    ... ADC performance. Operation to 300 MHz analog input is permitted, but it occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9269 can be used as a base- band or direct downconversion receiver, in which one ADC is used for I input data and the other is used for Q input data. ...

  • Page 20

    ... For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9269 (see Figure 40), and the 0.1µF 2V p-p P 0.1µF ANALOG INPUT ...

  • Page 21

    ... Figure 45), setting V C Differential (pF) 22 Open VIN+x If the internal reference of the AD9269 is used to drive multiple ADC converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 46 shows VIN–x how the internal reference voltage is affected by loading. ...

  • Page 22

    ... Jitter Considerations section. Figure 49 and Figure 50 show two preferred methods for clock- ing the AD9269 (at rates up to 6× the specified sample rate when using the internal clock divider function). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer ...

  • Page 23

    ... RESISTOR IS OPTIONAL. Figure 53. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Input Clock Divider The AD9269 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 6. Optimum performance is obtained by enabling the internal duty cycle stabilizer (DCS) when using divide ratios other than ...

  • Page 24

    ... Figure 55. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9269. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies ...

  • Page 25

    ... Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9269. These transients may degrade converter dynamic performance. The lowest typical conversion rate of the AD9269 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance may degrade. Data Clock Output (DCO) The AD9269 provides two data clock output (DCO) signals that are designed to capture the data in an external register ...

  • Page 26

    ... BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9269 signal path. Perform the BIST test after a reset to ensure that the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...

  • Page 27

    ... CHANNEL/CHIP SYNCHRONIZATION The AD9269 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock ...

  • Page 28

    ... LO leakage (dc) correction are still performed, but changes are no longer tracked. Bits[5:3] in Register 0x110 disable the respective correction when frozen. The default configuration on the AD9269 has the QEC and dc correction blocks disabled, and Bits[2:0] in Register 0x110 must be pulled high to enable the correction blocks. The quadrature ...

  • Page 29

    ... The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD9269. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 30

    ... If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9269 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SDIO/DCS and SCLK/DFS serve a dual function when the SPI interface is not being used ...

  • Page 31

    ... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9269 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). ...

  • Page 32

    ... Open 0x0B Clock divider (global) Bit 6 Bit 5 Bit 4 Bit 3 LSB Soft reset 1 1 first 8-bit chip ID, Bits[7:0] AD9269 = 0x75 Speed grade ID, Bits[6:4] 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Open Open Open Open Open Open Open Open External pin function ...

  • Page 33

    ... 0x00 B10 B9 B8 0x00 Open Open B0 0x00 AD9269 Comments When set, the test data is placed on the output pins in place of normal data When Bit 0 is set, the BIST function is initiated Device offset trim Configures the outputs and the format of the data ...

  • Page 34

    ... AD9269 Addr. Register (MSB) (Hex) Name Bit 7 0x2A Features Open 0x2E Output assign Open Digital feature control 0x100 Sync control Open (global) 0x101 USR2 Enable OEB (Pin 47) (local) 0x110 QEC Control 0 Open 0x111 QEC Control 1 0x112 QEC gain bandwidth control 0x113 ...

  • Page 35

    ... QEC Initial QEC Initial (Register 0x11C and Register 0x11D) Bits[13:0]—Initial DC Q When the force dc bit (Register 0x111, Bit 2) is set high, these values are used for dc error correction. Rev Page AD9269 ...

  • Page 36

    ... The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 41. RBIAS The AD9269 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...

  • Page 37

    ... AD9269BCPZRL7-40 –40°C to +85°C 2 AD9269BCPZ-20 –40°C to +85°C 2 AD9269BCPZRL7-20 –40°C to +85°C AD9269-80EBZ AD9269-65EBZ AD9269-40EBZ AD9269-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. 9.00 BSC SQ ...

  • Page 38

    ... AD9269 NOTES Rev Page ...

  • Page 39

    ... NOTES Rev Page AD9269 ...

  • Page 40

    ... AD9269 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08538-0-1/10(0) Rev Page ...