AD6642

Manufacturer Part NumberAD6642
DescriptionDual IF Receiver
ManufacturerAnalog Devices
AD6642 datasheet
 
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FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer (NSR)
Performance with NSR enabled
SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
SFDR: 83 dBc to 70 MHz @ 185 MSPS
Low power: 0.62 W @ 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Dual IF Receiver
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
DRGND
AD6642
14
VIN+A
PIPELINE
NOISE SHAPING
ADC
REQUANTIZER
VIN–A
VCMA
14
VIN+B
PIPELINE
NOISE SHAPING
ADC
REQUANTIZER
VIN–B
VCMB
REFERENCE
SERIAL PORT
SCLK
SDIO
CSB
Figure 1.
PRODUCT HIGHLIGHTS
1.
Two ADCs are contained in a small, space-saving,
10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.
2.
Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 60 MHz at 185 MSPS.
3.
LVDS digital output interface configured for low cost
FPGA families.
4.
120 mW per ADC core power consumption.
5.
Operation from a single 1.8 V supply.
6.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary or twos complement), NSR, power-down,
test modes, and voltage reference mode.
7.
On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2009–2010 Analog Devices, Inc. All rights reserved.
AD6642
DC0±AB
11
D0±AB
11
D10±AB
MODE
CLOCK
SYNC
DIVIDER
PDWN
CLK+
CLK–
www.analog.com

AD6642 Summary of contents

  • Page 1

    ... On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. AD6642 DC0±AB 11 D0±AB 11 D10±AB MODE ...

  • Page 2

    ... AD6642 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Specifications .................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 15 Theory of Operation ...

  • Page 3

    ... For example, with a sample clock rate of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode. ...

  • Page 4

    ... AD6642 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless S otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL) MATCHING CHARACTERISTIC Offset Error ...

  • Page 5

    ... Full −82 −90 25°C −95 25°C 82 Full 95 25°C 800 Rev Page AD6642 Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits ...

  • Page 6

    ... AD6642 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless S otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range High Level Input Voltage ...

  • Page 7

    ... Temperature Min Typ Full Full 40 185 Full 2.7 Full 1.3 Full 0.13 Full 3.0 4.35 Full 3.2 4.55 Full −0.4 −0.2 Full 9 Full 12 Full 1.2 Full 2 Rev Page AD6642 Max Unit kΩ pF 2.1 V 0.6 V −134 μA +10 μA kΩ pF 454 mV 1.375 V Max Unit 625 MHz 200 MSPS rms 5.7 ns 5.9 ns ...

  • Page 8

    ... AD6642 TIMING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless S otherwise noted. Table 5. Parameter Description SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC ...

  • Page 9

    ... Table 8. Package Type 144-Ball CSP_BGA × (BC-144-1) ESD CAUTION Rev Page AD6642 is specified for addi Airflow Velocity θ 1 θ ...

  • Page 10

    ... AD6642 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND DNC B AGND AGND C DNC AGND D DNC DNC E AGND AVDD F AGND AGND G DRGND DRGND H DRVDD DRVDD J DNC DNC K DNC DNC L DNC DNC M DNC DNC Table 9. Pin Function Descriptions Pin No. Mnemonic A5, A8, B5, B6, B7, B8, AVDD ...

  • Page 11

    ... Data Clock LVDS Output for Channel A and Channel B—Complement Input Mode Select Pin (Logic Low Enables NSR; Logic High Disables NSR) Input Digital Synchronization Pin Input Power-Down Input (Active High) Input SPI Clock Input/Output SPI Data Input SPI Chip Select (Active Low) Rev Page AD6642 ...

  • Page 12

    ... AD6642 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, T otherwise noted SNR = 65.7dB (66.7dBFS) –20 SFDR = 89.7dBc –40 –60 SECOND –80 HARMONIC –100 –120 FREQUENCY (MHz) Figure 5. Single-Tone FFT with f ...

  • Page 13

    ... SAMPLE RATE (MSPS) with f = 70.1 MHz 185MSPS 169.1MHz @ –7dBFS IN1 f = 172.1MHz @ –7dBFS IN2 SFDR = 81.8dBc FREQUENCY (MHz) = 169.1 MHz and f = 172.1 MHz IN1 IN2 AD6642 300 ) IN 250 ) S 90 ...

  • Page 14

    ... AD6642 0 –20 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 169.1 MHz and f = 172.1 MHz IN1 IN2 1,200,000 1,000,000 800,000 600,000 400,000 ...

  • Page 15

    ... Rev Page 350Ω SCLK OR 30kΩ PDWN Figure 26. Equivalent SCLK and PDWN Input Circuit AVDD 30kΩ 350Ω CSB OR MODE Figure 27. Equivalent CSB and MODE Input Circuit DRVDD 350Ω SDIO 30kΩ Figure 28. Equivalent SDIO Circuit AD6642 ...

  • Page 16

    ... ADC core. The span of the ADC core is set by this buffer to 2 × V Input Common Mode The analog inputs of the AD6642 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. An on-board common-mode voltage reference is included in the design and is available from the VCMx pins ...

  • Page 17

    ... ADA4938-2 provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCMx pin of the AD6642 (see Figure 30), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 15pF 200Ω ...

  • Page 18

    ... Figure 35. Active Front-End Configuration Using the AD8376 Figure 37 and Figure 38 show two preferred methods for clock- ing the AD6642 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer. ...

  • Page 19

    ... CLK+ Input Clock Divider 100Ω ADC 0.1µF The AD6642 contains an input clock divider with the ability to CLK– 240Ω divide the input clock by integer values from The AD6642 clock divider can be synchronized using the external SYNC input. Bit 1 of Register 0x3A enables the clock divider to be resynchronized on every SYNC signal ...

  • Page 20

    ... See the Memory Map Register Descriptions section for more details. CHANNEL/CHIP SYNCHRONIZATION The AD6642 has a SYNC input that offers the user flexible syn- chronization options for synchronizing the clock divider. The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The SYNC input is internally synchronized to the sample clock ...

  • Page 21

    ... AD6642. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6642 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD6642 provides a data clock output (DCO) signal intended for capturing the data in an external register. The output data for Channel A is valid when DCO is high ...

  • Page 22

    ... CENTER 0 ADC 0.22 × ADC Figure 45 to Figure 47 show the typical spectrum that can be expected from the AD6642 in the 22% BW mode for three different tuning words 184.32MSPS NSR 22% BW MODE –20 SNR = 73.4dB (75dBFS) (IN-BAND) SFDR = 92.6dBc (IN-BAND) – ...

  • Page 23

    ... Figure 48 to Figure 50 show the typical spectrum that can be expected from the AD6642 in the 33% BW mode for three different tuning words 184.32MSPS 140MHz @ –1.6dBFS IN NSR 33% BW MODE –20 SNR = 71dB (72.5dBFS) (IN-BAND) SFDR = 92.5dBc (IN-BAND) –40 –60 – ...

  • Page 24

    ... AD6642. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD6642 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops ...

  • Page 25

    ... Note AN-877, Interfacing to High Speed ADCs via SPI. CONFIGURATION USING THE SPI Three pins define the SPI of the AD6642: SCLK, SDIO, and CSB (see Table 12). SCLK (a serial clock) is used to synchronize the read and write data presented from and to the AD6642. SDIO (serial data input/output bidirectional pin that allows data to be sent to and read from the internal memory map registers ...

  • Page 26

    ... Address 0x13), this address location should not be written. Default Values After the AD6642 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 13). Logic Levels An explanation of logic level terminology follows: • ...

  • Page 27

    ... Open Open (global) 0x0C Shuffle mode Open Open (local) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID, Bits[7:0] AD6642 = 0x7A (default) Open Open Open Open Open Open Open Open External Open Open Open power- down pin function (global) ...

  • Page 28

    ... AD6642 Addr. Register (MSB) (Hex) Name Bit 7 Bit 6 0x0D Test mode Open Open (local) 0x0E BIST enable Open Open (local) 0x10 Offset adjust Open Open (local) 0x14 Output mode Open Open (local) 0x15 Output adjust Open Open (local) 0x16 Clock phase ...

  • Page 29

    ... For either mode, each step represents 0.5% of the ADC sample rate. For the equations used to calculate the tuning word based on the BW mode of operation, see the Noise Shaping Requantizer (NSR) section. Rev Page AD6642 Default (LSB) Value Bit 1 ...

  • Page 30

    ... AD6642 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting the design and layout of the AD6642 in a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD6642 recommended that two separate 1 ...

  • Page 31

    ... Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board Rev Page CORNER INDEX AREA DETAIL A 1.00 0.85 COPLANARITY SEATING 0.12 MAX PLANE Package Option BC-144-1 BC-144-1 AD6642 ...

  • Page 32

    ... AD6642 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08563-0-7/10(A) Rev Page ...