AD6642 Analog Devices, AD6642 Datasheet - Page 11

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AD6642

Manufacturer Part Number
AD6642
Description
Dual IF Receiver
Manufacturer
Analog Devices
Datasheet

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Pin No.
K8
J8
M8
L8
K9
J9
M9
L9
K10
J10
M10
L10
K11
J11
M11
L11
K12
J12
M12
L12
C9
C8
C7
C6
C5
C4
Mnemonic
D2+AB
D2−AB
D3+AB
D3−AB
D4+AB
D4−AB
D5+AB
D5−AB
D6+AB
D6−AB
D7+AB
D7−AB
D8+AB
D8−AB
D9+AB
D9−AB
D10+AB
D10−AB
DCO+AB
DCO−AB
MODE
SYNC
PDWN
SCLK
SDIO
CSB
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input/Output
Input
Rev. A | Page 11 of 32
Channel A and Channel B LVDS Output Data 2—Complement
Channel A and Channel B LVDS Output Data 3—True
Channel A and Channel B LVDS Output Data 3—Complement
Channel A and Channel B LVDS Output Data 4—Complement
Channel A and Channel B LVDS Output Data 5—True
Channel A and Channel B LVDS Output Data 5—Complement
Channel A and Channel B LVDS Output Data 6—True
Channel A and Channel B LVDS Output Data 6—Complement
Channel A and Channel B LVDS Output Data 7—True
Channel A and Channel B LVDS Output Data 7—Complement
Channel A and Channel B LVDS Output Data 8—True
Channel A and Channel B LVDS Output Data 8—Complement
Channel A and Channel B LVDS Output Data 9—True
Channel A and Channel B LVDS Output Data 9—Complement
Channel A and Channel B LVDS Output Data 10—True
Channel A and Channel B LVDS Output Data 10—Complement
Mode Select Pin (Logic Low Enables NSR; Logic High Disables NSR)
Digital Synchronization Pin
SPI Clock
SPI Chip Select (Active Low)
Description
Channel A and Channel B LVDS Output Data 2—True
Channel A and Channel B LVDS Output Data 4—True
Data Clock LVDS Output for Channel A and Channel B—True
Data Clock LVDS Output for Channel A and Channel B—Complement
Power-Down Input (Active High)
SPI Data
AD6642

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