AD6642 Analog Devices, AD6642 Datasheet - Page 18

• Manufacturer Part Number: AD6642
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

AD6642
For the popular IF band of 140 MHz, Figure 34 shows an
example of a 1:4 transformer passive configuration where a
differential inductor is used to resonate with the internal input
capacitance of the AD6642. This configuration realizes excellent
noise and distortion performance. Figure 35 shows an example
of an active front-end configuration using the
VGA. This configuration is recommended when signal gain
is required.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6642 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 36) and require no external bias.
Clock Input Options
The AD6642 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern (see the Jitter Considerations section).
CLK+
Figure 36. Equivalent Clock Input Circuit
2pF
AVDD
1.2V
ANALOG
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
Z = 50Ω
INPUT
INPUT
AD8376
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
0.1µF
Figure 35. Active Front-End Configuration Using the AD8376
XFMR 1:4 Z
ETC4-1T-7
1µH
1µH
AD8376
2pF
Figure 34. 1:4 Transformer Passive Configuration
1000pF
1000pF
CLK–
VPOS
0.1µF
1nF
0.1µF
0.1µF
dual
0.1µF
301Ω
180nH
180nH
Rev. A | Page 18 of 32
121Ω
121Ω
5.1pF
220nH
220nH
3.9pF
33Ω
33Ω
165Ω
165Ω
Figure 37 and Figure 38 show two preferred methods for clock-
ing the AD6642 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer config-
uration is recommended for clock frequencies from 10 MHz to
200 MHz. The back-to-back Schottky diodes across the trans-
former/balun secondary limit clock excursions into the AD6642
to approximately 0.8 V p-p differential.
This limit helps to prevent the large voltage swings of the clock
from feeding through to other portions of the AD6642 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
CLOCK
431nH
INPUT
AIN–
CLOCK
VCM
15pF
INPUT
1nF
Figure 37. Transformer-Coupled Differential Clock (Up to 200 MHz)
3.0kΩ
Figure 38. Balun-Coupled Differential Clock (Up to 625 MHz)
VCM
68nH
50Ω
0.1µF
50Ω
3.0pF
3.0kΩ║3.0pF
1nF
AD6642
INTERNAL
1nF
INPUT Z
100Ω
ADC
ADT1-1WT, 1:1Z
0.1µF
XFMR
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
CLK+
CLK–
CLK+
CLK–
ADC
ADC