AD6642 Analog Devices, AD6642 Datasheet - Page 30

• Manufacturer Part Number: AD6642
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

AD6642
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting the design and layout of the AD6642 in a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD6642, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). The AVDD and DRVDD supplies should be isolated
with separate decoupling capacitors. Several different decoupling
capacitors can be used to cover both high and low frequencies.
These capacitors should be located close to the point of entry
at the PCB level and close to the pins of the part, with minimal
trace length.
A single PCB ground plane should be sufficient when using the
AD6642. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
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VCMx Pins
The VCMx pins are provided to set the common-mode level
of the analog inputs. The VCMx pins should be decoupled to
ground with a 0.1 μF capacitor, as shown in Figure 31.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the AD6642 is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade AD6642 performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6642 to prevent these signals from transi-
tioning at the receiver inputs during critical sampling periods.