AD7194 Analog Devices, AD7194 Datasheet - Page 20

• Manufacturer Part Number: AD7194
• Description: 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7194

• Resolution (bits): 24bit
• # Chan: 8
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7194
STATUS REGISTER
RS2, RS1, RS0 = 000; Power-On/Reset = 0x80
The status register is an 8-bit read-only register. To access the
ADC status register, the user must write to the communications
register, select the next operation to be a read operation, and
SR7
RDY(1)
Table 18. Status Register (SR) Bit Designations
Bit Location
SR7
SR6
SR5
SR4
SR3 to SR0
RDY
ERR
NOREF
Parity
CHD3 to CHD0
Bit Name
SR6
ERR(0)
SR5
NOREF(0)
Description
Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set
automatically after the ADC data register is read, or a period of time before the data register is updated,
with a new conversion result to indicate to the user that the conversion data should not be read. It is
also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end
of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the
status register for monitoring the ADC for conversion data.
ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the
result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange,
underrange, or the absence of a reference voltage. This bit is cleared when the result written to the data
register returns to within the allowed analog input range. The ERR bit is also set during calibrations if
the reference source is invalid or if the applied analog input voltages are outside range during system
calibrations.
No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a
voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is
cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled
by setting the REFDET bit in the configuration register to 1.
Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is
an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data
register. The DAT_STA bit in the mode register should be set when the parity check is used. When the
DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data
register read.
These bits indicate which channel corresponds to the data register contents. They do not indicate
which channel is presently being converted, but indicate which channel was selected when the
conversion contained in the data register was generated.
SR4
Parity(0)
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SR3
CHD3(0)
load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 18 outlines the bit
designations for the status register. SR0 through SR7 indicate the
bit locations, SR denoting that the bits are in the status register.
SR7 denotes the first bit of the data stream. The number in paren-
theses indicates the power-on/reset default status of that bit.
SR2
CHD2(0)
SR1
CHD1(0)
SR0
CHD0(0)