AD7194 Analog Devices, AD7194 Datasheet - Page 22

• Manufacturer Part Number: AD7194
• Description: 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7194

• Resolution (bits): 24bit
• # Chan: 8
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7194
Bit Location
MR12
MR11
MR10
MR9 to MR0
Bit Name
CLK_DIV
Single
REJ60
FS9 to FS0
Description
Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this
bit to 0. When performing internal full-scale calibrations, this bit must be set when AV
4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used
while performing the calibration. When AV
the CLK_DIV bit when performing internal full-scale calibrations.
Single cycle conversion enable bit. When this bit is set, the AD7194 settles in one conversion cycle so
that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are
enabled or when the single conversion mode is selected. If the fast-settling filter is enabled, this bit
(single) does not have an effect on the conversions unless chopping is also enabled.
This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a
filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/
60 Hz rejection.
Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter
cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In
association with the gain selection, they also determine the output noise and, therefore, the effective
resolution of the device (see Table 6 through Table 11).
When chop is disabled, fast settling mode is disabled and continuous conversion mode is selected
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and
MCLK is the master clock frequency.
With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop
disabled and fast settling mode disabled, the first notch frequency is equal to the output data rate when
converting on a single channel.
When chop is enabled (fast settling mode disabled)
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and
MCLK is the master clock frequency.
With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N
is the order of the sinc filter. The first notch frequency of the sinc filter is equal to
The chopping introduces notches at odd integer multiples of
Output Data Rate = (MCLK/1024)/FS
Output Data Rate = (MCLK/1024)/(N × FS)
N × Output Data Rate
Output Data Rate/2
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DD
is greater than or equal to 4.75 V, it is not compulsory to set
DD
is less than