AD7194 Analog Devices, AD7194 Datasheet - Page 28

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AD7194

Manufacturer Part Number
AD7194
Description
8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
Manufacturer
Analog Devices
Datasheet

Specifications of AD7194

Resolution (bits)
24bit
# Chan
8
Sample Rate
n/a
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref/PGA Gain) p-p
Adc Architecture
Sigma-Delta
Pkg Type
CSP

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AD7194
OFFSET REGISTER
RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000)
The offset register holds the offset calibration coefficient for the
ADC. The power-on reset value of the offset register is 0x800000.
The register is a 24-bit read/write register. It is used in conjunc-
tion with the full-scale register to form a register pair. The
power-on reset value is automatically overwritten if an internal
or system zero-scale calibration is initiated by the user. The
AD7194 must be placed in power-down mode or idle mode
when writing to the offset register.
Rev. 0 | Page 28 of 56
FULL-SCALE REGISTER
RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0
The full-scale register is a 24-bit register that holds the full-scale
calibration coefficient for the ADC. The full-scale register is
a read/write register. However, when writing to the full-scale
register, the ADC must be placed in power-down mode or idle
mode. The register is configured at power-on with a factory
calibrated full-scale calibration coefficient, the calibration being
performed at gain = 1. Therefore, every device has different
default coefficients. The default value is automatically over-
written if an internal or system full-scale calibration is initiated
by the user or if the full-scale register is written to.

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