AD7194 Analog Devices, AD7194 Datasheet - Page 34

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AD7194

Manufacturer Part Number
AD7194
Description
8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
Manufacturer
Analog Devices
Datasheet

Specifications of AD7194

Resolution (bits)
24bit
# Chan
8
Sample Rate
n/a
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref/PGA Gain) p-p
Adc Architecture
Sigma-Delta
Pkg Type
CSP

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Manufacturer
Quantity
Price
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Manufacturer:
ADI/亚德诺
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AD7194
Continuous Conversion Mode
Continuous conversion is the default power-up mode. The
AD7194 converts continuously, and the RDY bit in the status
register goes low each time a conversion is complete. If CS is
low, the DOUT/ RDY line also goes low when a conversion is
completed. To read a conversion, the user writes to the commu-
nications register, indicating that the next operation is a read of
the data register. When the data-word has been read from the
data register, DOUT/ RDY goes high. The user can read this
DOUT/RDY
SCLK
DIN
CS
0x58
Figure 25. Continuous Conversion
Rev. 0 | Page 34 of 56
DATA
register additional times, if required. However, the user must
ensure that the data register is not being accessed at the com-
pletion of the next conversion or else the new conversion word
is lost.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The status register indi-
cates the channel to which the conversion corresponds.
0x58
DATA

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