AD7194 Analog Devices, AD7194 Datasheet - Page 38

• Manufacturer Part Number: AD7194
• Description: 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7194

• Resolution (bits): 24bit
• # Chan: 8
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7194
An internal zero-scale calibration, system zero-scale calibration,
and system full-scale calibration can be performed at any
output data rate. An internal full-scale calibration can be
performed at any output data rate for which the filter word,
FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent
of the 10-bit word written to Bit FS9 to Bit FS0 in the mode
register. Therefore, internal full-scale calibrations can be
performed at output data rates such as 10 Hz or 50 Hz when
chop is disabled. Using these lower output data rates results in
better calibration accuracy.
The offset error is, typically, ±150 μV/gain. If the gain is changed, it
is advisable to perform a calibration. A zero-scale calibration (an
internal zero-scale calibration or a system zero-scale calibration)
reduces the offset error to the order of the noise.
The gain error of the AD7194 is factory calibrated at a gain of 1
with a 5 V power supply at ambient temperature. Following this
calibration, the gain error is ±0.001%, typically, at 5 V. Table 27
shows the typical uncalibrated gain error for the different gain
settings.
Table 27. Typical Precalibration Gain Error vs. Gain
Gain
8
16
32
64
128
Precalibration Gain Error (%)
−0.11
−0.20
−0.23
−0.29
−0.4
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An internal full-scale calibration reduces the gain error to
±0.001%, typically, when the gain is equal to 1. For higher gains,
the gain error post internal full-scale calibration is ±0.003%,
typically when AV
AV
calibration is ±0.005%, typically.
When AV
when performing internal full-scale calibrations. This increases
the calibration time by a factor of 2. The accuracy of the internal
full-scale calibration is further increased if chop is enabled and
a low output data rate is used while performing the calibration.
A system full-scale calibration reduces the gain error to the
order of the noise irrespective of the analog power supply
voltage.
The AD7194 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the calibration
coefficients of the device and also to write its own calibration
coefficients from prestored values in the EEPROM. A read of
the registers can be performed at any time. However, the ADC
must be placed in power-down or idle mode when writing to
the registers. The values in the calibration registers are 24 bits
wide. The span and offset of the part can also be manipulated
using the registers.
DD
is less than 4.75 V, the gain error post internal full-scale
DD
is less than 4.75 V, the CLK_DIV bit must be set
DD
is equal to or higher than 4.75 V. When