AD7194 Analog Devices, AD7194 Datasheet - Page 7

• Manufacturer Part Number: AD7194
• Description: 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7194

• Resolution (bits): 24bit
• # Chan: 8
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

TIMING CHARACTERISTICS
AV
Table 2.
Parameter
READ AND WRITE OPERATIONS
READ OPERATION
WRITE OPERATION
1
2
3
4
5
6
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 3 and Figure 4.
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V
The SCLK active edge is the falling edge of SCLK.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
t
t
t
t
t
t
t
t
t
t
t
DD
3
4
1
2
5
6
7
8
9
10
11
3
5, 6
= 3 V to 5.25 V,
DV
DD
= 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 =
Limit at T
100
100
0
60
80
0
60
80
10
80
0
10
0
30
25
0
MIN
, T
MAX
(B Version)
Rev. 0 | Page 7 of 56
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
R
= t
F
= 5 ns (10% to 90% of DV
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
CS falling edge to DOUT/RDY active time
DV
DV
DV
DV
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
CS falling edge to SCLK active edge setup time
CS rising edge to SCLK edge hold time
SCLK active edge to data valid delay
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
DD
DD
DD
DD
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
DD
) and timed from a voltage level of 1.6 V.
DV
OL
DD
or V
1, 2
, unless otherwise noted.
OH
limits.
4
AD7194
4