AD7626 Analog Devices, AD7626 Datasheet - Page 23

• Manufacturer Part Number: AD7626
• Description: 16-Bit, 10 MSPS, PulSAR Differential ADC
• Manufacturer: Analog Devices

Specifications of AD7626

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 10MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP

Self-Clocked Mode
The digital operation of the AD7626 in self-clocked interface
mode is shown in Figure 42. This interface mode reduces the
number of traces between the ADC and the digital host to two
LVDS pairs (CLK± and D±) or to a single pair if sharing a
common CLK±. Multiple AD7626 devices can share a common
CLK± signal. This can be useful in reducing the number of
LVDS connections to the digital host.
When the self-clocked interface mode is used, each ADC
data-word is preceded by a 010 sequence. The first zero is
automatically on D± once t
is then clocked out by the first two CLK± falling edges. This
header is used to synchronize D± of each conversion in the
digital host because, in this mode, there is no data clock output
synchronous to the data (D±) to allow the digital host to
acquire the data output.
Synchronization of the D± data to the digital host’s acquisition
clock is accomplished by using one state machine per AD7626
device. For example, using a state machine that runs at the
same speed as CLK± incorporates three phases of this clock
frequency (120º apart). Each phase acquires the data D± as
output by the ADC.
CNV–
CNV+
CLK–
CLK+
D+
D–
t
CLKD
ACQUISITION
t
CLK
SAMPLE N
MSB
t
CNVH
has elapsed. The 2-bit header
17
N – 1
D1
t
MSB
18
N – 1
D0
Figure 42. Self-Clocked Interface Mode Timing Diagram
t
CYC
0
ACQUISITION
1
Rev. A | Page 23 of 2
1
2
SAMPLE N + 1
0
3
D15
N
The AD7626 data captured on each phase of the state
machine clock is then compared. The location of the 1 in
the header in each set of data acquired allows the user to
choose the state machine clock phase that occurs during
the data valid window of D±.
The self-clocked mode data capture method allows the digital
host to adapt its result capture timing to accommodate
variations in propagation delay through any AD7626.For
example, where data is captured from multiple AD7626s
sharing a common input clock.
Conversions are initiated by a CNV± pulse. The CNV± pulse
must be returned low (t
After a conversion begins, it continues until completion.
Additional CNV± pulses are ignored during the conversion
phase. After the time, t
the CLK± signal to the AD7626. All 18 CLK± pulses are to be
applied in the time window framed by t
t
(referenced to the next conversion phase) elapses. Otherwise,
the data is lost because it is overwritten by the next conversion
result.
Set CLK± to idle high between bursts of 18 CLK± pulses. The
header bit and conversion data of the next ADC result are
output on subsequent falling edges of CLK± during the next
burst of the CLK± signal.
CLKL
4
D14
. The required 18 CLK± pulses must finish before t
N
t
CLKL
17
D1
N
18
MSB
D0
CNVH
N
, elapses, the host begins to burst
maximum) for valid operation.
0
ACQUISITION
1
1
MSB
and the subsequent
2
0
3
N + 1
D15
AD7626
CLKL