AD9265 Analog Devices, AD9265 Datasheet - Page 30

• Manufacturer Part Number: AD9265
• Description: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9265

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9265
CLOCK
CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, drive the CLK+ pin directly from a CMOS gate, and bypass
the CLK− pin to ground with a 0.1 μF capacitor (see Figure 79).
CLOCK
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9265 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide a
wide range of clock input duty cycles without affecting the perfor-
mance of the AD9265. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS enabled.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 μs to 5 μs is required after a dynamic clock frequency increase
or decrease before the DCS loop is relocked to the input signal.
During the time period that the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the duty
cycle of the input clock signal. In such applications, it may be
appropriate to disable the duty cycle stabilizer. The DCS can also be
disabled in some cases when using the input clock divider circuit,
see the Input Clock Divider section for additional information. In
all other applications, enabling the DCS circuit is recommended
to maximize ac performance.
1
INPUT
INPUT
INPUT
50Ω RESISTOR IS OPTIONAL.
Figure 78. Differential LVDS Sample Clock (Up to Rated Sample Rate)
Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50Ω
0.1µF
1
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
AD95xx
LVDS DRIVER
AD95xx
CMOS DRIVER
OPTIONAL
0.1µF
100Ω
100Ω
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9265
AD9265
ADC
ADC
Rev. A | Page 30 of 44
The DCS is enabled by setting the SDIO/DCS pin high when
operating in the external pin mode (see Table 12). If the SPI
mode is enabled, the DCS is enabled by default and can be
disabled by writing a 0x00 to Address 0x09.
Input Clock Divider
The AD9265 contains an input clock divider with the ability to
divide the input clock by integer values between 2 and 8. For
clock divide ratios of 2, 4, 6, or 8, the duty cycle stabilizer (DCS)
is not required because the output of the divider inherently
produces a 50% duty cycle. Enabling the DCS with the clock
divider in these divide modes may cause a slight degradation
in SNR; therefore, disabling the DCS is recommended. For
other divide ratios, divide-by-3, divide-by-5, and divide-by-7,
the duty cycle output from the clock divider is related to the
input clock’s duty cycle. In these modes, if the input clock has
a 50% duty cycle, the DCS is again not required. However, if a
50% duty cycle input clock is not available, the DCS must be
enabled for proper part operation.
The AD9265 clock divider can be synchronized using an external
sync signal applied to the SYNC pin input. Bit 1 and Bit 2 of Reg-
ister 0x100 allow the clock divider to be resynchronized on every
SYNC signal or only on the first SYNC signal after the register
is written. A valid signal at the SYNC pin causes the clock divider
to reset to its initial state. This synchronization feature allows
multiple parts to have their clock dividers aligned to guarantee
simultaneous input sampling. If the SYNC pin is not used, it
should be tied to AGND.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low frequency
SNR (SNR
can be calculated by
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 80.
SNR
80
75
70
65
60
55
50
1
HF
LF
= −10 log[(2π × f
) at a given input frequency (f
MEASURED
Figure 80. SNR vs. Input Frequency and Jitter
INPUT FREQUENCY (MHz)
10
INPUT
× t
JRMS
INPUT
)
100
2
+ 10
) due to jitter (t
(

SNR
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
LF
/
10
)
1k
]
JRMS
)