AD9609

Manufacturer Part NumberAD9609
Description10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9609 datasheet
 


Specifications of AD9609

Resolution (bits)10bit# Chan1
Sample Rate80MSPSInterfacePar
Analog Input TypeDiff-UniAin Range2 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
61.5 dBFS at 9.7 MHz input
61.0 dBFS at 200 MHz input
SFDR
75 dBc at 9.7 MHz input
73 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
76 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.10 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
AVDD
RBIAS
VCM
VIN+
VIN–
VREF
SENSE
REF
SELECT
CLK+ CLK–
PRODUCT HIGHLIGHTS
1.
The AD9609 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D9 to D0) timing and offset adjustments, and voltage
reference modes.
4.
The AD9609 is packaged in a 32-lead RoHS compliant
LFCSP that is pin compatible with the
and the
AD9649
path between 10-bit and 14-bit converters sampling from
20 MSPS to 80 MSPS.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9609
GND
SDIO SCLK CSB
DRVDD
SPI
OR
PROGRAMMING DATA
D9 (MSB)
ADC
CORE
D0 (LSB)
DCO
AD9609
DIVIDE
MODE
DCS
BY
CONTROLS
1 TO 8
PDWN
DFS MODE
Figure 1.
AD9629
12-bit ADC
14-bit ADC, enabling a simple migration
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.

AD9609 Summary of contents

  • Page 1

    ... SENSE REF SELECT CLK+ CLK– PRODUCT HIGHLIGHTS 1. The AD9609 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...

  • Page 2

    ... Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 11 AD9609-80 .................................................................................. 11 AD9609-65 .................................................................................. 13 AD9609-40 .................................................................................. 14 AD9609-20 .................................................................................. 15 Equivalent Circuits ......................................................................... 16 Theory of Operation ...................................................................... 17 Analog Input Considerations .................................................... 17 REVISION HISTORY 10/09—Revision 0: Initial Version Voltage Reference ....................................................................... 19 Clock Input Considerations ...................................................... 20 Power Dissipation and Standby Mode .................................... 22 Digital Outputs ...

  • Page 3

    ... GENERAL DESCRIPTION The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and- hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range ...

  • Page 4

    ... Rev Page AD9609-65 AD9609-80 Typ Max Min Typ Max 10 Guaranteed Guaranteed +0.05 +0.55 −0.45 +0.05 +0.55 −1.5 −1.5 ±0.25 ±0.25 ±0.15 ±0.07 ±0.45 ±0.45 ±0.15 ±0.15 ±2 ±2 0.996 1.008 0.984 0.996 1.008 2 2 0.08 0.08 2 ...

  • Page 5

    ... Full −67 25°C −82 Full 25°C 25°C 78 25°C 80.5 Full 67 25°C 78 Full 25°C 25°C −82 25°C −82 Full −74 25°C −82 Full 25°C 25°C 25°C 700 Rev Page AD9609 AD9609-65 AD9609-80 Min Typ Max Min Typ Max 61.5 61.5 61.5 61.5 61.0 61.5 61.5 61.0 61.0 61.0 61.4 61.4 61.3 61.4 60.5 61.4 61.4 60 9.9 9.9 9.9 9.9 9.9 9.9 9 ...

  • Page 6

    ... High Level Output Voltage 0 Low Level Output Voltage 1 Low Level Output Voltage μ Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. AD9609-20/AD9609-40/AD9609-65/AD9609-80 Temp Min Typ CMOS/LVDS/LVPECL Full 0.9 Full 0.2 Full GND − 0.3 Full −10 Full − ...

  • Page 7

    ... Rev Page AD9609-65 AD9609-80 Min Typ Max Min Typ 625 15.38 12.5 7.69 6.25 1.0 1.0 0.1 0 0.1 0 350 350 300 260 – – – 4 AD9609 Max Unit 625 MHz 80 MSPS rms Cycles μs ns Cycles ...

  • Page 8

    ... AD9609 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the SCLK CLK t Setup time between CSB and SCLK ...

  • Page 9

    ... ESD CAUTION Rev Page Airflow Velocity θ θ θ (m/sec 37.1 3.1 20.7 1.0 32.4 2.5 29.1 is specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD9609 Ψ 1,2 Unit JT 0.3 °C/W 0.5 °C/W 0.8 °C/W ...

  • Page 10

    ... VIN−, VIN+ ADC Analog Inputs. CLK AVDD PIN 1 CLK– MODE/OR INDICATOR AVDD 3 22 DCO CSB (MSB) AD9609 SCLK/DFS TOP VIEW SDIO/PDWN (Not to Scale NOTES CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS ...

  • Page 11

    ... IN 0 80MSPS 200MHz @ –1dBFS SNR = 60.1dB (60.1dBFS) SFDR = 74.176dBc FREQUENCY (MHz) Figure 8. AD9609-80 Single-Tone FFT with f = 200 MHz IN –10 –30 SFDR (dBc) IMD3 (dBc) –50 –70 SFDR (dBFS) –90 IMD3 (dBFS) –60 –54 –48 –42 –36 – ...

  • Page 12

    ... DCS disabled, unless otherwise noted SFDR (dBc SNR (dBFS 100 AIN FREQUENCY (MHz) Figure 10. AD9609-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 85 SFDR (dBc SNR (dBFS SAMPLE RATE (MHz) Figure 11 ...

  • Page 13

    ... Figure 18.AD9609-65 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz Figure 19. AD9609-65 SNR/SFDR vs. Input Frequency (AIN) with = 70.3 MHz 30.5 MHz IN Rev Page AD9609 SFDR (dBc) IMD3 (dBc) SFDR (dBFS) IMD3 (dBFS) –54 –48 –42 –36 – ...

  • Page 14

    ... FREQUENCY (MHz) Figure 21. AD9609-40 Single-Tone FFT with Figure 22. AD9609-40 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz 30.5 MHz IN Rev Page SFDRFS SNRFS SFDR SNR 0 –60 –50 –40 –30 –20 INPUT AMPLITUDE (dBc) – ...

  • Page 15

    ... Figure 24. AD9609-20 Single-Tone FFT with –60 = 9.7 MHz Figure 25. AD9609-20 SNR/SFDR vs. Input Amplitude (AIN) with 30.5 MHz IN Rev Page AD9609 SFDR (dBFS) SNR (dBFS) SFDR (dBc) SNR (dBc) –10 –50 –40 –30 –20 ...

  • Page 16

    ... AD9609 EQUIVALENT CIRCUITS AVDD VIN± Figure 26. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 27. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 28. Equivalent SENSE Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 29. Equivalent Clock Input Circuit 375Ω ...

  • Page 17

    ... Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The analog inputs of the AD9609 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is ...

  • Page 18

    ... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9609 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...

  • Page 19

    ... ADC can be varied by configuring SPI Address 0x18 as shown in Table 11, resulting in a selectable differential span from p-p. If the internal reference of the AD9609 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 43 shows how the internal reference voltage is affected by loading ...

  • Page 20

    ... Jitter Considerations section. Figure 46 and Figure 47 show two preferred methods for clock- ing the AD9609 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun. ...

  • Page 21

    ... The clock input should be treated as an analog signal when aperture jitter may affect the dynamic range of the AD9609. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources ...

  • Page 22

    ... CLOCK RATE (MSPS) Figure 53. AD9609 Analog Core Power vs. Clock Rate In SPI mode, the AD9609 can be placed in power-down mode directly via the SPI port using the programmable external MODE pin. In non-SPI mode, power-down is achieved by assert- ing the PDWN pin high. In this state, the ADC typically dissipates 500 μ ...

  • Page 23

    ... VIN+ − VIN− = +VREF − 1.0 LSB VIN+ − VIN− > +VREF − 0.5 LSB The lowest typical conversion rate of the AD9609 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD9609 provides a data clock output (DCO) signal intended for capturing the data in an external register ...

  • Page 24

    ... BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9609 signal path. Perform the BIST test after a reset to ensure that the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...

  • Page 25

    ... SERIAL PORT INTERFACE (SPI) The AD9609 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

  • Page 26

    ... The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD9609. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 27

    ... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9609 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). ...

  • Page 28

    ... Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Soft 1 1 Soft LSB reset reset first 8-bit chip ID, Bits[7:0] AD9609 = 0x71 Open Open Open Open Open Open Open Open Open 00 = chip run 01 = full power-down 10 = standby 11 = chip wide digital reset Open Open ...

  • Page 29

    ... USER_PATT1_MSB B15 B14 0x1B USER_PATT2_LSB B7 B6 0x1C USER_PATT2_MSB B15 B14 0x24 BIST signature LSB 0x2A OR/MODE select Open Open 1.1. AD9609-Specific Customer SPI Control 0x101 USR2 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Open Open Open BIST Open INIT Open Output Open Output ...

  • Page 30

    ... AD9609 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. USR2 (Register 0x101) Bit 3—Enable GCLK Detect Normally set high, this bit enables a circuit that detects encode rates below about 5 MSPS ...

  • Page 31

    ... APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9609 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9609 strongly recom- mended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD) ...

  • Page 32

    ... AD9609BCPZRL7-40 –40°C to +85° AD9609BCPZ-20 –40°C to +85° AD9609BCPZRL7-20 –40°C to +85°C 1 AD9609-80EBZ AD9609-65EBZ 1 1 AD9609-40EBZ 1 AD9609-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ...