AD9609 Analog Devices, AD9609 Datasheet - Page 23

• Manufacturer Part Number: AD9609
• Description: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9609

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

TIMING
The AD9609 provides latched data with a pipeline delay of
eight clock cycles. Data outputs are available one propagation
delay (t
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9609. These
transients can degrade converter dynamic performance.
Table 13. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
PD
) after the rising edge of the clock signal.
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
00 0000 0000
00 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
Rev. 0 | Page 23 of 32
The lowest typical conversion rate of the AD9609 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9609 provides a data clock output (DCO) signal
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 for a
graphical timing description.
Twos Complement Mode
10 0000 0000
10 0000 0000
00 0000 0000
01 1111 1111
01 1111 1111
AD9609
OR
1
0
0
0
1