AD9629

Manufacturer Part NumberAD9629
Description12-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9629 datasheet
 


Specifications of AD9629

Resolution (bits)12bit# Chan1
Sample Rate80MSPSInterfacePar
Analog Input TypeDiff-UniAin Range2 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
71.3 dBFS at 9.7 MHz input
69.0 dBFS at 200 MHz input
SFDR
95 dBc at 9.7 MHz input
83 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
85 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.16 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Integer 1, 2, or 4 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
AVDD
RBIAS
VCM
VIN+
VIN–
VREF
SENSE
REF
SELECT
CLK+ CLK–
PRODUCT HIGHLIGHTS
1.
The AD9629 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3.
A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO and data
output (D11 to D0) timing and offset adjustments, and
voltage reference modes.
4.
The AD9629 is packaged in a 32-lead RoHS compliant LFCSP
that is pin compatible with the
the
AD9649
14-bit ADC, enabling a simple migration path
between 10-bit and 14-bit converters sampling from 20 MSPS
to 80 MSPS.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9629
GND
SDIO SCLK CSB
DRVDD
SPI
OR
PROGRAMMING DATA
D11 (MSB)
ADC
CORE
D0 (LSB)
DCO
AD9629
DIVIDE BY
MODE
1, 2, 4
CONTROLS
PDWN
DFS MODE
Figure 1.
AD9609
10-bit ADC and
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.

AD9629 Summary of contents

  • Page 1

    ... SENSE REF SELECT CLK+ CLK– PRODUCT HIGHLIGHTS 1. The AD9629 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...

  • Page 2

    ... Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 11 AD9629-80 .................................................................................. 11 AD9629-65 .................................................................................. 13 AD9629-40 .................................................................................. 14 AD9629-20 .................................................................................. 15 Equivalent Circuits ......................................................................... 16 Theory of Operation ...................................................................... 17 Analog Input Considerations .................................................... 17 REVISION HISTORY 10/09—Revision 0: Initial Version Voltage Reference ....................................................................... 19 Clock Input Considerations ...................................................... 20 Power Dissipation and Standby Mode .................................... 21 Digital Outputs ...

  • Page 3

    ... GENERAL DESCRIPTION The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital conver- ter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range ...

  • Page 4

    ... Rev Page AD9629-80 Typ Max Min Typ Max 12 Guaranteed +0.05 +0.50 −0.40 +0.05 +0.50 −1.5 −1.5 ±0.25 ±0.30 ±0.11 ±0.16 ±0.30 ±0.35 ±0.13 ±0.16 ±2 ±2 0.996 1.008 0.984 0.996 1.008 2 2 0.25 0. ...

  • Page 5

    ... Full 83 25°C 96/94 Full 25°C 83 25°C −100 25°C −100 Full −92/−91 25°C −97/−100 Full 25°C −92 25°C 90 25°C 700 Rev Page AD9629 AD9629-65 AD9629-80 Min Typ Max Min Typ Max 71.3 71.3 71.2 71.2 70.6 71.0 70.9 70.3 69.0 69.0 71.3 71.2 71.2 71.1 70.5 70.9 70.8 70 11.6 11.5 11.5 11.5 11 ...

  • Page 6

    ... High Level Output Voltage 0 Low Level Output Voltage 1 Low Level Output Voltage μ Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. AD9629-20/AD9629-40/AD9629-65/AD9629-80 Temp Min Typ CMOS/LVDS/LVPECL Full 0.9 Full 0.2 Full GND − 0.3 Full −10 Full − ...

  • Page 7

    ... Rev Page AD9629-65 AD9629-80 Min Typ Max Min Typ 260 15.38 12.5 7.69 6.25 1.0 1.0 0.1 0 0.1 0 350 350 300 260 – – – 4 AD9629 Max Unit 320 MHz 80 MSPS rms Cycles μs ns Cycles ...

  • Page 8

    ... AD9629 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the SCLK CLK t Setup time between CSB and SCLK ...

  • Page 9

    ... ESD CAUTION Rev Page Airflow Velocity (m/sec) θ θ θ 37.1 3.1 20.7 1.0 32.4 2.5 29.1 is specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD9629 1, 2 Ψ Unit JT 0.3 °C/W 0.5 °C/W 0.8 °C/W ...

  • Page 10

    ... VIN−, VIN+ ADC Analog Inputs. CLK AVDD PIN 1 CLK– MODE/OR INDICATOR AVDD 3 22 DCO CSB 4 21 D11 (MSB) AD9629 SCLK/DFS 5 20 D10 TOP VIEW SDIO/PDWN (Not to Scale NOTES CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS ...

  • Page 11

    ... FREQUENCY (MHz) Figure 8. AD9629-80 Single-Tone FFT with –20 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) and ...

  • Page 12

    ... AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 100 SFDR 90 80 SNR 100 INPUT FREQUENCY (MHz) Figure 10. AD9629-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 100 90 SFDR 80 SNRFS SAMPLE RATE (MHz) Figure 11 ...

  • Page 13

    ... FREQUENCY (MHz) Figure 17. AD9629-65 Single-Tone FFT with 9.7 MHz Figure 18. AD9629-65 SNR/SFDR vs. Input Amplitude (AIN) with MHz 30.6 MHz IN Rev Page 120 ...

  • Page 14

    ... FREQUENCY (MHz) Figure 21. AD9629-40 Single-Tone FFT with f 120 100 9.7 MHz Figure 22. AD9629-40 SNR/SFDR vs. Input Amplitude (AIN) with 30.6 MHz IN Rev Page SFDRFS SNRFS SFDR SNR 0 –70 –60 –50 –40 –30 – ...

  • Page 15

    ... FREQUENCY (MHz) Figure 24. AD9629-20 Single-Tone FFT with f 120 100 –70 = 9.7 MHz Figure 25. AD9629-20 SNR/SFDR vs. Input Amplitude (AIN) with 30.6 MHz IN Rev Page AD9629 SFDRFS SNRFS SFDR SNR –60 –50 –40 –30 –20 –10 INPUT AMPLITUDE (dBc) ...

  • Page 16

    ... AD9629 EQUIVALENT CIRCUITS AVDD VIN± Figure 26. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 27. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 28. Equivalent SENSE Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 29. Equivalent Clock Input Circuit 375Ω ...

  • Page 17

    ... Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The analog inputs of the AD9629 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 ...

  • Page 18

    ... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9629 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...

  • Page 19

    ... SELECT LOGIC SENSE Figure 42. Internal Reference Configuration If the internal reference of the AD9629 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 43 shows how the internal reference voltage is affected by loading. 0 –0.5 –1.0 INTERNAL VREF = 0.996V – ...

  • Page 20

    ... Jitter Considerations section. Figure 46 and Figure 47 show two preferred methods for clock- ing the AD9629. The CLK inputs support up to 4× the rated sample rate when using the internal clock divider feature. A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun. ® ...

  • Page 21

    ... Figure 52. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9629. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies ...

  • Page 22

    ... Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9629. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9629 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD9629 provides a data clock output (DCO) signal intended for capturing the data in an external register ...

  • Page 23

    ... AD9629. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9629 signal path. Perform the BIST test after a reset to ensure the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...

  • Page 24

    ... AD9629 SERIAL PORT INTERFACE (SPI) The AD9629 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

  • Page 25

    ... The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9629. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 26

    ... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9629 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 16). ...

  • Page 27

    ... Offset adjust Offset adjust in LSBs from +127 to −128 (twos complement format) Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset 8-bit chip ID, Bits[7:0] AD9629 = 0x70 Open Open Open Open Open Open Open Open Open Clock divider, Bits[2:0] Clock divide ratio 000 = divide-by-1 ...

  • Page 28

    ... USER_PATT1_MSB B15 B14 0x1B USER_PATT2_LSB B7 B6 0x1C USER_PATT2_MSB B15 B14 0x24 BIST signature LSB 0x2A OR/MODE select Open Open 1.1. AD9629 Specific Customer SPI Control 0x101 USR2 1 Open Bit 5 Bit 4 Bit 3 Bit 2 Open Output Open Output disable invert 1.8 V DCO 3.3 V data drive strength ...

  • Page 29

    ... GCLK detector. Bit 0—Disable SDIO Pull-Down This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. Rev Page AD9629 ...

  • Page 30

    ... The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 38. RBIAS The AD9629 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...

  • Page 31

    ... AD9629BCPZ-20 –40°C to +85° AD9629BCPZRL7-20 –40°C to +85°C 1 AD9629-80EBZ AD9629-65EBZ 1 1 AD9629-40EBZ 1 AD9629-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ...

  • Page 32

    ... AD9629 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08540-0-10/09(0) Rev Page ...