AD9629 Analog Devices, AD9629 Datasheet - Page 19

• Manufacturer Part Number: AD9629
• Description: 12-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9629

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9629. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections
that follow. The Reference Decoupling section describes the
best practices PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9629 detects the potential at the
SENSE pin and configures the reference into two possible modes,
which are summarized in Table 10. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 42), setting VREF to 1.0 V.
If the internal reference of the AD9629 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 43 shows
how the internal reference voltage is affected by loading.
Table 10. Reference Configuration Summary
Selected Mode
Fixed Internal Reference
Fixed External Reference
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
0
1.0µF
0.2
Figure 42. Internal Reference Configuration
Figure 43. VREF Accuracy vs. Load Current
0.4
0.1µF
SENSE
VREF
VIN+
VIN–
0.6
LOAD CURRENT (mA)
INTERNAL VREF = 0.996V
0.8
1.0
SELECT
LOGIC
SENSE Voltage (V)
AGND to 0.2
AVDD
1.2
ADC
0.5V
1.4
CORE
ADC
1.6
1.8
Resulting VREF (V)
1.0 internal
1.0 applied to external VREF pin
2
.0
Rev. 0 | Page 19 of 32
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 44 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 27). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
–1
–2
–3
–4
–5
–6
4
3
2
1
0
–40
–20
Figure 44. Typical VREF Drift
Resulting Differential Span (V p-p)
2.0
2.0
VREF ERROR (mV)
0
TEMPERATURE (°C)
20
40
60
AD9629
80