AD9649 Analog Devices, AD9649 Datasheet - Page 27

• Manufacturer Part Number: AD9649
• Description: 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9649

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Addr.
(Hex)
Chip configuration registers
0x00
0x01
0x02
Device transfer registers
0xFF
Program registers
0x08
0x0B
0x0D
0x0E
0x10
Register Name
SPI port
configuration
Chip ID
Chip grade
Transfer
Modes
Clock divide
Test mode
BIST enable
Offset adjust
External
Pin 23
MODE
input
enable
User test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
(MSB)
Bit 7
0
Open
Open
Open
Bit 6
LSB first
Open
External Pin 23
function when high
00 = full power-down
01 = standby
10 = normal mode,
output disabled
11 = normal mode,
output enabled
Open
(identify device variants of chip ID)
Offset adjust in LSBs from +127 to −128 (twos complement format)
Speed grade ID, Bits[6:4]
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
8-bit device offset adjustment, Bits[7:0] (local)
Open
Reset PN
long gen
Bit 5
Soft
reset
Open
Open
8-bit chip ID, Bits[7:0]
Bit 4
1
Open
Open
Reset PN
short
gen
Open
Rev. 0 | Page 27 of 32
AD9649 = 0x6F
Bit 3
1
Open
Open
Open
Output test mode, Bits[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = 1/0 word toggle
1000 = user input
1001 = 1/0 bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
Bit 2
reset
Open
Open
BIST init
Soft
Clock divider, Bits[2:0]
Open
000 = divide-by-1
001 = divide-by-2
011 = divide-by-4
Clock divide ratio
Bit 1
LSB first
Open
00 = chip run
01 = full power-down
10 = standby
11 = chip wide
digital reset
Open
(LSB)
Bit 0
0
Transfer
BIST
enable
Def.
Value
(Hex)
0x18
Read
only
Read
only
0x00
0x00
0x00
0x00
0x00
0x00
Default
Notes/
Comments
The nibbles are
mirrored so that
LSB or MSB first
mode registers
correctly, regard-
less of shift
mode.
Unique chip ID
used to differen-
tiate devices;
read only.
Unique speed
grade ID used to
differentiate
devices; read
only.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.
The divide ratio
is the value + 1.
When set, the
test data is
placed on the
output pins in
place of normal
data.
When Bit 0 is set,
the built-in self-
test function is
initiated.
Device offset
trim.
AD9649