AD9649 Analog Devices, AD9649 Datasheet - Page 7

• Manufacturer Part Number: AD9649
• Description: 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9649

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period, Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Wake-Up Time
Standby
2
1
A
)
CLK+
CLK–
DATA
DCO
SKEW
VIN
CH
)
)
PD
DCO
)
)
J
)
CLK
)
N – 1
t
CH
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
t
Min
50/25
PD
3
N
AD9649-20/AD9649-40
Figure 2. CMOS Output Data Timing
t
t
A
CLK
t
DCO
t
SKEW
N – 8
Typ
25.0/12.5
1.0
0.1
3
3
0.1
8
350
600/400
2
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N + 1
N – 7
Max
80/160
20/40
N + 2
N – 6
Min
3
15.38
N + 3
AD9649-65
Typ
7.69
1.0
0.1
3
3
0.1
8
350
300
2
N – 5
N + 4
Max
260
65
Min
3
12.5
N – 4
N + 5
AD9649-80
Typ
6.25
1.0
0.1
3
3
0.1
8
350
260
2
Max
320
80
AD9649
Unit
MHz
MSPS
ns
ns
ns
ps rms
ns
ns
ns
Cycles
μs
ns
Cycles