AD7193

Manufacturer Part NumberAD7193
Description4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
ManufacturerAnalog Devices
AD7193 datasheet
 


Specifications of AD7193

Resolution (bits)24bit# Chan4
Sample Raten/aInterfaceSer,SPI
Analog Input TypeDiff-Uni,SE-Uni,Usr-Defined Range/OffsetAin Range± (Vref/Gain)
Adc ArchitectureSigma-DeltaPkg TypeSOP
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Page 1/56

Download datasheet (2Mb)Embed
Next
Data Sheet
FEATURES
Fast settling filter option
4 differential/8 pseudo differential input channels
RMS noise: 11 nV @ 4.7 Hz (gain = 128)
15.5 noise-free bits @ 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Specified drift over time
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AV
: 3 V to 5.25 V
DD
DV
: 2.7 V to 5.25 V
DD
Current: 4.65 mA
Temperature range: −40°C to +105°C
28-lead TSSOP and 32-lead LFCSP packages
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
PLC/DCS analog input modules
Data acquisition
Strain gage transducers
AV
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AINCOM
BPDSW
AGND
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
4-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
Pressure measurement
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7193 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
The device can be configured to have four differential inputs or
eight pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled simultaneously, and the
AD7193 sequentially converts on each enabled channel, simplifying
communication with the part. The on-chip 4.92 MHz clock can
be used as the clock source to the ADC or, alternatively, an external
clock or crystal can be used. The output data rate from the part
can be varied from 4.7 Hz to 4.8 kHz.
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. The AD7193 also
includes a zero latency option.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.65 mA, and it is available in a 28-lead
TSSOP package and a 32-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
AGND
DV
DGND
REFIN1(+)
REFIN1(–)
DD
DD
AD7193
Σ-Δ
MUX
PGA
ADC
TEMP
SENSOR
CLOCK
CIRCUITRY
MCLK1 MCLK2
P0/REFIN2(–) P1/REFIN2(+)
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD7193
DOUT/RDY
SERIAL
INTERFACE
DIN
AND
CONTROL
SCLK
LOGIC
CS
SYNC
P3
P2
www.analog.com
©2009–2011 Analog Devices, Inc. All rights reserved.

AD7193 Summary of contents

  • Page 1

    ... Chromatography Medical and scientific instrumentation GENERAL DESCRIPTION The AD7193 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC ...

  • Page 2

    ... AD7193 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings .......................................................... 10 Thermal Resistance .................................................................... 10 ESD Caution ................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 RMS Noise and Resolution............................................................ 18 Sinc 4 Chop Disabled ................................................................... 18 Sinc Chop Disabled ................................................................... 19 3 Fast Settling ................................................................................. 20 On-Chip Registers ...

  • Page 3

    ... Changes to Offset Register and Full-Scale Register Sections .... 29 Changes to Reference Section ....................................................... 31 Changes to Data Output Coding Section .................................... 32 Changes to Sinc 4 50 Hz/60 Hz Rejection Section ....................... 41 Changes to Sinc 50 Hz/60 Hz Rejection Section ....................... 43 3 Changes to 50 Hz/60 Hz Rejection, Sinc Changes to Summary of Filter Options Section and Table 7/09—Revision 0: Initial Version Rev Page AD7193 4 Filter Section ............ 47 ...

  • Page 4

    ... AD7193 SPECIFICATIONS 5. 2 5.25 V, AGND = DGND = 0 V; REFINx(+) = 2 MCLK = 4.92 MHz unless otherwise noted. A MIN MAX Table 1. Parameter Min ADC Output Data Rate 4.7 1.17 1. Missing Codes 24 24 Resolution RMS Noise and Output Data Rates Integral Nonlinearity ...

  • Page 5

    ... Rev Page AD7193 Test Conditions/Comments output data rate ± ± output data rate, REJ60 ± ± output data rate ± output data rate ± ...

  • Page 6

    ... AD7193 Parameter Min REFERENCE INPUT REFIN Voltage 1 Absolute REFIN Voltage AGND − 0.05 2 Limits Average Reference Input Current Average Reference Input Current Drift 2 Normal Mode Rejection Common-Mode Rejection Reference Detect Levels 0.3 TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH Allowable Current BURNOUT CURRENTS ...

  • Page 7

    ... Rev Page AD7193 Test Conditions/Comments 1 Gain = 1, buffer off Gain = 1, buffer on Gain = 8, buffer off Gain = 8, buffer on Gain = 16 to 128, buffer off Gain = 16 to 128, buffer External crystal used Power-down mode ...

  • Page 8

    ... AD7193 TIMING CHARACTERISTICS 5. 2 5.25 V, AGND = DGND = 0 V, Input Logic Input Logic Table 2. Parameter Limit at T READ AND WRITE OPERATIONS t 100 3 t 100 4 READ OPERATION ...

  • Page 9

    ... Data Sheet DOUT/RDY (O) SCLK (I) SCLK ( MSB INPUT OUTPUT Figure 3. Read Cycle Timing Diagram CS ( DIN (I) MSB LSB I = INPUT OUTPUT Figure 4. Write Cycle Timing Diagram Rev Page LSB AD7193 ...

  • Page 10

    ... AD7193 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AV to AGND AGND DD AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AINx/Digital Input Current Operating Temperature Range Storage Temperature Range ...

  • Page 11

    ... Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected ...

  • Page 12

    ... Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7193 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state low ...

  • Page 13

    ... AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as DD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is DD Rev Page − − AD7193 and DD and DD , but DD ...

  • Page 14

    ... Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected ...

  • Page 15

    ... REF 0 200 400 600 SAMPLE = Output Data Rate = 42.1 Hz (FS[9: REF DD Average by 16), Gain = 1, Chop Disabled, Sinc 200 150 100 50 0 8,388,864 8,388,868 8,388,872 8,388,876 CODE = Output Data Rate = REF DD AD7193 8,388,920 = Filter) 800 1000 4 Filter) 8,388,880 4 Filter) ...

  • Page 16

    ... AD7193 –1 –2 –4 –3 –2 – (V) IN Figure 13. INL (Gain = –5 –10 –15 –20 –0.03 –0.02 –0. (V) IN Figure 14. INL (Gain = 128) 170 168 166 164 162 160 158 156 154 –60 – ...

  • Page 17

    ... REF (V GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 1k 10k = 5 V) REF Rev Page GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 10 100 OUTPUT DATA RATE (Hz) Figure 21. Noise Free Resolution in Fast Settling Mode = 5 V, Averaging by 16, Sinc 4 Filter, Chop Disabled) REF AD7193 1k ...

  • Page 18

    ... AD7193 RMS NOISE AND RESOLUTION The following tables show the rms noise, peak-to-peak noise, effective resolution, and noise free (peak-to-peak) resolution of the AD7193 for various output data rates and gain settings with chop disabled for the sinc 4 and sinc ...

  • Page 19

    ... Gain (21.4) 23.9 (21.2) 23.5 (20.9) 23.9 (21.1) 23.6 (20.9) 23.2 (20.6) 23.7 (20.9) 23.4 (20.7) 23 (20.3) 22.9 (20.1) 22.5 (19.7) 22 (19.3) 22.7 (20) 22.3 (19.6) 21.9 (19.1) 22 (19.3) 21.8 (19) 21.2 (18.4) 21.6 (18.8) 21.2 (18.5) 20.7 (17.9) 20.3 (17.6) 20.1 (17.4) 19.6 (16.9) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) AD7193 128 160 950 7000 128 65 88 100 230 250 390 560 1100 6100 45,000 128 22.8 (20.2) 22.4 (19.8) 22.2 (19.6) 21.1 (18.4) 21 (18.3) 20.3 (17.6) 19.8 (17.1) 18.9 (16.1) 16.4 (13.6) 13.5 (10.7) ...

  • Page 20

    ... AD7193 FAST SETTLING Table 13. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data (Decimal) Average Rate ( 42. 50. 126. 252.63 Table 14. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data ...

  • Page 21

    ... OF13 OF12 OF7 OF6 OF5 OF4 FS23 (MSB) FS22 FS21 FS20 FS15 FS14 FS13 FS12 FS7 FS6 FS5 FS4 Rev Page AD7193 Bit 3 Bit 2 Bit 1 Bit 0 CREAD 0 0 CHD3 CHD2 CHD1 CHD0 CLK1 CLK0 AVG1 AVG0 Single REJ60 FS9 FS8 ...

  • Page 22

    ... AD7193 COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communi- cations register determine whether the next operation is a read or write operation and in which register this operation occurs. For ...

  • Page 23

    ... SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in paren- theses indicates the power-on/reset default status of that bit. SR4 SR3 SR2 Parity(0) CHD3(0) CHD2(0) Rev Page AD7193 SR1 SR0 CHD1(0) CHD0(0) ...

  • Page 24

    ... MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7193. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7193 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7193. ...

  • Page 25

    ... MR11 Single Single cycle conversion enable bit. When this bit is set, the AD7193 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. If the average + decimate filter is enabled, this bit (single) does not have an effect on the conversions unless chopping is also enabled ...

  • Page 26

    ... AD7193 MD2 MD1 MD0 Mode Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. ...

  • Page 27

    ... CON17 to CON8 Short, TEMP, Channel select bits. These bits select which channels are enabled on the AD7193 (see Table 23 and Table 24). CH7 to CH0 Several channels can be selected, and the AD7193 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected ...

  • Page 28

    ... AD7193 Bit Location Bit Name Description CON4 BUF Enables the buffer on the analog inputs. If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. When the buffer is enabled, it requires some head- room ...

  • Page 29

    ... LSBs of the status register (CHD3 to CHD0) identify the channel from which the conversion originated. ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX2 The identification number for the AD7193 is stored in the ID register. This is a read-only register. GP7 GP6 GP5 ...

  • Page 30

    ... The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7193 must be placed in power- down mode or idle mode when writing to the offset register. FULL-SCALE REGISTER RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC ...

  • Page 31

    ... Clock The AD7193 has an internal 4.92 MHz clock. Either this clock or an external clock can be used as the clock source to the AD7193. The internal clock can also be made available on a pin if a clock source is required for external circuitry. ...

  • Page 32

    ... Hz, which is equivalent to 22.7 bits of effective resolution or 20 bits of noise free resolution. The AD7193 can be programmed to have a gain 16, 32, 64, or 128 by using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 19. 2.5 V, and the bipolar ranges are from ± ...

  • Page 33

    ... AIN1 pin is 2 3.75 V when a 2.5 V reference is used. If AINCOM is 2.5 V and the AD7193 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1. 3.75 V. The bipolar/unipolar option is chosen by programming the U/ B bit in the configuration register ...

  • Page 34

    ... Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7193 using CS to decode the part. Figure 3 shows the timing for a read operation from the output shift register of the AD7193, and Figure 4 shows the timing for a write operation to ADC the input shift register ...

  • Page 35

    ... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7193 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface is lost due to a software error or a glitch in the system ...

  • Page 36

    ... AD7193 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7193 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the commu- nications register, indicating that the next operation is a read of the data register ...

  • Page 37

    ... Data Sheet Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7193 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to the communi- cations register, the user need only apply the appropriate number ...

  • Page 38

    ... AD7193 into a consistent, known state. While the SYNC pin is low, the AD7193 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again ...

  • Page 39

    ... Data Sheet TEMPERATURE SENSOR Embedded in the AD7193 is a temperature sensor. This is selected using the TEMP bit in the configuration register. When the TEMP bit is set to 1, the temperature sensor is enabled. When the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 when the temperature is 0 Kelvin, theoretically ...

  • Page 40

    ... The gain error of the AD7193 is factory calibrated at a gain of 1 with power supply at ambient temperature. Following this calibration, the gain error is, typically, ±0.001 Table 27 shows the typical uncalibrated gain error for the different gain settings ...

  • Page 41

    ... Data Sheet DIGITAL FILTER The AD7193 offers a lot of flexibility in the digital filter. The device has five filter options. The device can be operated with a sinc 3 or sinc 4 filter, chop can be enabled or disabled, and zero latency can be enabled. Finally, an averaging block can be included after the sinc filter, which gives a fast settling mode. ...

  • Page 42

    ... AD7193 When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process ...

  • Page 43

    ... Output Data Rate (Hz ADC CHANNEL B CHANNEL A CHANNEL ADC 3 Figure 37. Sinc Channel Change ANALOG INPUT ADC OUTPUT f 1/ ADC Figure 38. Asynchronous Step Change in Analog Input AD7193 Settling Time (ms) 300 FULLY SETTLED ...

  • Page 44

    ... The user does not need to consider the effects of channel changes on the output data rate. When the channel sequencer is enabled, the AD7193 automatically operates in zero latency mode. The output data rate equals ...

  • Page 45

    ... Rev Page FILTER) ADC 3 4 CHOP MODULATOR SINC /SINC POST FILTER Figure 44. Chop Enabled 4 4 filter, the output data rate is equal /(4 × 1024 × FS[9:0]) ADC CLK = 2/f SETTLE ADC Output Data Rate (Hz) 12.5 15 AD7193 Chop Enabled) Settling Time (ms) 160 133 ...

  • Page 46

    ... AD7193 When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f . ADC CHANNEL A CHANNEL CONVERSIONS Figure 45. Channel Change (Sinc ...

  • Page 47

    ... ADC OUTPUT f 1/ ADC is equal to 3dB f = 0.24 × f 3dB ADC 3 Chop Enabled) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 100 FREQUENCY (Hz) Figure 52. Sinc 3 Filter Response (FS[9:0] = 96, Chop Enabled) AD7193 3 Chop Enabled) /2. The notches ADC 125 150 ...

  • Page 48

    ... AD7193 The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 53 is achieved. The output data rate is unchanged but the 50 Hz/60 Hz ± rejection improves typically. ...

  • Page 49

    ... Figure 60. Filter Response for Average + Decimate Filter 120 150 Rev Page AD7193 120 FREQUENCY (Hz) (Sinc 4 Filter, FS[9:0] = 30, Average by 16 120 FREQUENCY (Hz) (Sinc 4 Filter, FS[9:0] = 96, Average by 16) 150 ...

  • Page 50

    ... AD7193 FAST SETTLING MODE (SINC 3 FILTER) In fast settling mode, the settling time is close to the inverse of the first filter notch. Therefore, the user can achieve 50 Hz and/ rejection at an output data rate close to 1/ 1/60 Hz. The settling time is equal to 1/output data rate. Therefore, the conversion time is constant when converting on a single channel or when converting on several channels ...

  • Page 51

    ... SETTLE 120 150 Consequently, if chop is enabled, the sinc is set to 6, averaging enabled, and the output data rate is equal to 42.1 Hz. Therefore, the conversion time equals 1/42. 23.75 ms, and the settling time is equal to 47.5 ms. Rev Page AD7193 120 FREQUENCY (Hz) 3 (Sinc ...

  • Page 52

    ... AD7193 SUMMARY OF FILTER OPTIONS The AD7193 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, and the 50 Hz/60 Hz rejection. Table 36. Filter Summary 1 Filter FS[9:0] Sinc 4 , Chop Disabled 4 1 Sinc 4 , Chop Disabled 5 Sinc 3 , Chop Disabled ...

  • Page 53

    ... AD7193 to prevent noise coupling. The power supply lines to the AD7193 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs ...

  • Page 54

    ... FLOWMETER Figure 68 shows the AD7193 being used in a flowmeter application that consists of two pressure transducers with the rate of flow being equal to the pressure difference. The pressure transducers are arranged in a bridge network and give a differential output voltage between its OUT+ and OUT− ...

  • Page 55

    ... PLANE ORDERING GUIDE Model 1 Temperature Range AD7193BRUZ −40°C to +105°C AD7193BRUZ-REEL −40°C to +105°C AD7193BCPZ −40°C to +105°C AD7193BCPZ-RL −40°C to +105°C AD7193BCPZ-RL7 −40°C to +105°C EVAL-AD7193EBZ Evaluation Board Z = RoHS Compliant Part. 1 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1 ...

  • Page 56

    ... AD7193 NOTES ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08367-0-12/11(C) Rev Page Data Sheet ...