AD7193 Analog Devices, AD7193 Datasheet - Page 27

• Manufacturer Part Number: AD7193
• Description: 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7193

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni,Usr-Defined Range/Offset
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

Data Sheet
CONFIGURATION REGISTER
RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117
The configuration register is a 24-bit register from which data
can be read or to which data can be written. This register is
used to configure the ADC for unipolar or bipolar mode, to
enable or disable the buffer, to enable or disable the burnout
currents, to select the gain, and to select the analog input channel.
CON23
Chop(0)
CON15
CH7(0)
CON7
Burn(0)
Table 22. Configuration Register (CON) Bit Designations
Bit Location
CON23
CON22, CON21
CON20
CON19
CON18
CON17 to CON8
CON7
CON6
CON5
CON22
0(0)
CON14
CH6(0)
CON6
REFDET(0)
CH7 to CH0
Bit Name
Chop
0
REFSEL
0
Pseudo
Short, TEMP,
Burn
REFDET
0
Description
Chop enable bit.
When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed.
For an FS word of 96 decimal and the sinc
time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and
offset drift.
When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC
are continuously removed. However, this increases the conversion time and settling time of the ADC.
For example, when FS = 96 decimal and the sinc
enabled equals 80 ms and the settling time equals 160 ms.
These bits must be programmed with a Logic 0 for correct operation.
Reference select bits. The reference source for the ADC is selected using these bits.
REFSEL
0
1
This bit must be programmed with a Logic 0 for correct operation.
Pseudo differential analog inputs. The analog inputs can be configured as differential inputs or pseudo
differential analog inputs. When the pseudo bit is set to 1, the AD7193 is configured to have eight
pseudo differential analog inputs. When pseudo bit is set to 0, the AD7193 is configured to have four
differential analog inputs.
Channel select bits. These bits select which channels are enabled on the AD7193 (see Table 23 and Table 24).
Several channels can be selected, and the AD7193 automatically sequences them. The conversion on
each channel requires the complete settling time. When performing calibrations or when accessing the
calibration registers, only one channel can be selected.
When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When burn = 0, the
burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and
when chop is disabled.
Enables the reference detect function. When set, the NOREF bit in the status register indicates when the
external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference
detect circuitry operates only when the ADC is active.
This bit must be programmed with a Logic 0 for correct operation.
CON21
0(0)
CON13
CH5(0)
CON5
0(0)
CON20
REFSEL(0)
CON12
CH4(0)
CON4
BUF(1)
Reference Voltage
External reference applied between REFIN1(+) and REFIN1(−).
External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins.
Rev. C | Page 27 of 56
CON19
0(0)
CON11
CH3(0)
CON3
U/B(0)
Table 22 outlines the bit designations for the configuration register.
CON0 through CON23 indicate the bit locations. CON denotes
that the bits are in the configuration register. CON23 denotes
the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit.
4
filter selected, the conversion time is 20 ms and the settling
4
filter is selected, the conversion time with chop
CON18
Pseudo(0)
CON10
CH2(0)
CON2
G2(1)
CON17
Short(0)
CON9
CH1(0)
CON1
G1(1)
CON16
TEMP(0)
CON8
CH0(1)
CON0
G0(1)
AD7193