AD7193 Analog Devices, AD7193 Datasheet - Page 43

• Manufacturer Part Number: AD7193
• Description: 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7193

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni,Usr-Defined Range/Offset
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

Data Sheet
Simultaneous 50 Hz/60 Hz rejection can also be achieved using
the REJ60 bit in the mode register. When FS[9:0] is set to 96
and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz.
The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 35 shows the
frequency response of the sinc
± 1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum,
assuming a stable 4.92 MHz master clock.
SINC
A sinc
selected using the SINC3 bit in the mode register. The sinc
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
Sinc
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
ADC
CLK
is the master clock (4.92 MHz nominal).
is the output data rate.
3
f
–100
–110
–120
ADC
–10
–20
–30
–40
–50
–60
–70
–80
–90
Output Data Rate and Settling Time
3
3
filter can be used instead of the sinc
0
FILTER (CHOP DISABLED)
0
= f
Figure 35. Sinc
CHOP
CLK
/(1024 × FS[9:0])
25
Figure 36. Sinc
MODULATOR
4
Filter Response (FS[9:0] = 96, REJ60 = 1)
50
FREQUENCY (Hz)
3
Filter (Chop Disabled)
4
ADC
SINC
filter. The filter provides 50 Hz
75
3
/SINC
4
100
4
POST FILTER
filter. The filter is
125
150
3
Rev. C | Page 43 of 56
The settling time is equal to
The 3 dB frequency is equal to
Table 30 gives some examples of FS settings and the corresponding
output data rates and settling times.
Table 30. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
480
96
80
When a channel change occurs, the modulator and filter reset. The
complete settling time is allowed to generate the first conversion
after the channel change (see Figure 37). Subsequent conversions
on this channel are available at 1/f
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input. Therefore, it continues to output conversions at
the programmed output data rate. However, it is at least three
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is processing
a conversion, the ADC takes four conversions after the step change
to generate a fully settled result.
CONVERSIONS
t
f
ANALOG
OUTPUT
3dB
SETTLE
CHANNEL
INPUT
= 0.272 × f
ADC
Figure 38. Asynchronous Step Change in Analog Input
= 3/f
CH A
Output Data Rate (Hz)
10
50
60
ADC
CHANNEL A
Figure 37. Sinc
ADC
CH A CH A
1/
f
3
ADC
Channel Change
ADC
.
1/
CHANNEL B
f
ADC
CH B
Settling Time (ms)
300
60
50
CH B
SETTLED
FULLY
CH B
AD7193
CH B