AD9251 Analog Devices, AD9251 Datasheet
AD9251
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AD9251 Summary of contents
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... VIN–B VIN+B CLK+ CLK– PRODUCT HIGHLIGHTS 1. The AD9251 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...
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... Timing Specifications .................................................................. 8 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 13 AD9251-80 .................................................................................. 13 AD9251-65 .................................................................................. 15 AD9251-40 .................................................................................. 16 AD9251-20 .................................................................................. 17 Equivalent Circuits ......................................................................... 18 Theory of Operation ...................................................................... 20 ADC Architecture ...................................................................... 20 Analog Input Considerations .................................................... 20 REVISION HISTORY 10/09—Rev Rev. A Changes to Features .......................................................................... 1 Change to Table 1 ............................................................................. 4 Moved Timing Diagrams................................................................. 8 Deleted Table 11 ...
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... ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus. The AD9251 is available in a 64-lead RoHS Compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). Rev Page ...
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... Rev Page AD9251-80 Typ Max Min Typ Max 14 Guaranteed ±0.1 ±0.50 ±0.1 ±0.70 −1.5 −1.5 ±0.75 ±0.70 ±0.45 ±0.45 ±1.75 ±2.50 ±0.6 ±1.0 ±0.0 ±0.65 ±0.0 ±0.65 ±0.2 ±0.2 ±2 ±2 0.993 1.005 ...
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... Full 81 81 25°C 93 Full 25°C 80 25°C −98 25°C −98 Full −90 25°C −98 Full 25°C −95 25°C 90 Full −110 25°C 700 Rev Page AD9251 AD9251-65 AD9251-80 Typ Max Min Typ Max 74.5 74.3 74.3 74.1 73.7 73.6 72.5 71.5 71.5 74.4 74.1 74.2 74.0 73.6 73.5 72.4 70.0 70.0 12.0 12.0 12.0 12.0 11.9 11.9 11.3 11.3 −95 −93 −95 − ...
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... High Level Output Voltage 0 Low Level Output Voltage 1 Low Level Output Voltage μ Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. AD9251-20/AD9251-40/AD9251-65/AD9251-80 Temp Min Full Full 0.2 Full GND − 0.3 Full −10 Full −10 Full ...
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... Full 3 Full 0.1 Full 9 Full 350 Full 600/400 Full 2 Rev Page AD9251-65 AD9251-80 Min Typ Max Min Typ 625 15.38 12.5 7.69 6.25 1.0 1.0 0.1 0 0.1 0 350 350 300 260 2 2 AD9251 Max Unit 625 MHz 80 MSPS rms Cycles μs ns Cycles ...
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... AD9251 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...
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... CLK SSYNC HSYNC SYNC Figure 4. SYNC Input Timing Requirements Rev Page AD9251 ...
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... AD9251 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND ...
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... Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high. 30 kΩ internal pull-down. Digital Input. 30 kΩ internal pull-down. PDWN high = power-down device. PDWN low = run device, normal operation. 1.8 V Analog Supply Pins. Channel A Analog Inputs. Rev Page AD9251 48 PDWN 47 OEB 46 CSB 45 ...
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... AD9251 Pin No. Mnemonic 55 VREF 56 SENSE 57 VCM 58 RBIAS 61, 62 VIN−B, VIN+B Description Voltage Reference Input/Output. Reference Mode Selection. Analog output voltage at midsupply to set common mode of the analog inputs. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. ...
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... Figure 10. Single-Tone FFT with f = 200 MHz IN 0 –20 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90 –78 –66 –54 –42 –30 INPUT AMPLITUDE (dBFS) 30.5 MHz and f = 32.5 MHz IN2 AD9251 –18 –6 = IN1 ...
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... AD9251 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 100 SFDR (dBc SNR (dBFS 100 INPUT FREQUENCY (MHz) Figure 12. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale ...
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... SFDRFS 100 80 SNRFS 60 SFDR 40 SNR 20 0 –90 –80 –60 –40 INPUT AMPLITUDE (dBFS) 100 90 SFDR (dBc SNR (dBFS 100 150 INPUT FREQUENCY (MHz) Figure 22. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale AD9251 – 9.7 MHz IN 200 ...
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... AD9251 AD9251-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 40MSPS 9.7MHz @ –1dBFS –15 SNR = 73.5dB (74.5dBFS) SFDR = 95.4dBc –30 –45 –60 –75 – –105 –120 FREQUENCY (MHz) Figure 23 ...
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... MHz Figure 28. SNR/SFDR vs. Input Amplitude (AIN) with 30.5 MHz IN Rev Page 120 SFDR (dBFS) 100 SNR (dBFS SFDR (dBc) 40 SNR (dBc –100 –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) AD9251 –20 – 9.7 MHz IN ...
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... AD9251 EQUIVALENT CIRCUITS AVDD VIN±x Figure 29. Equivalent Analog Input Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 30. Equivalent Clock Input Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ Figure 31. Equivalent SDIO/DCS Input Circuit 0.9V Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Rev ...
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... DRVDD AVDD 30kΩ 350Ω CSB Figure 35. Equivalent CSB Input Circuit AVDD 375Ω SENSE Figure 36. Equivalent SENSE Circuit VREF Figure 37. Equivalent VREF Circuit Rev Page AD9251 AVDD 375Ω 7.5kΩ ...
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... ADC performance. Operation to 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9251 can be used as a base- band or direct downconversion receiver, where one ADC is used for I input data and the other is used for Q input data. ...
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... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9251 (see Figure 41), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... AD9251 Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common- mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 43 shows a typical single-ended input configuration. ...
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... SENSE Voltage (V) Fixed Internal Reference AGND to 0.2 Fixed External Reference AVDD If the internal reference of the AD9251 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 47 shows how the internal reference voltage is affected by loading. ADC CORE 0 ...
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... Jitter Considerations section. Figure 50 and Figure 51 show two preferred methods for clock- ing the AD9251 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun. ...
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... RESISTOR IS OPTIONAL. Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Input Clock Divider The AD9251 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. clock drivers offer Optimum performance is obtained by enabling the internal duty cycle stabilizer (DCS) when using divide ratios other than ...
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... Note available on www.analog.com for more information. CHANNEL/CHIP SYNCHRONIZATION The AD9251 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock ...
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... Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9251. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9251 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Data Clock Output (DCO) ...
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... AD9251. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9251 signal path. Perform the BIST test after a reset to ensure the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...
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... SERIAL PORT INTERFACE (SPI) The AD9251 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9251. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9251 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 16). ...
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... Name (MSB) Chip Configuration Registers 0x00 SPI port 0 configuration (global) 0x01 Chip ID (global) 8-bit chip ID bits [7:0] AD9251 = 0x23 0x02 Chip grade Open (global) Device Index and Transfer Registers 0x05 Channel index Open 0xFF Transfer Open Program Registers (May or May Not Be Indexed by Device Index) ...
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... B10 B9 B8 0x00 0x00 B10 B9 B8 0x00 Open Open B0 0x00 AD9251 Comments When set, the test data is placed on the output pins in place of normal data When Bit 0 is set, the BIST function is initiated Device offset trim Configures the outputs and the format of ...
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... AD9251 Address Register Bit 7 (Hex) Name (MSB) 0x2A Features Open 0x2E Output assign Open Digital Feature Control 0x100 Sync control Open (global) 0x101 USR2 Enable OEB Pin 47 (local) MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Note, Interfacing to High Speed ADCs via SPI ...
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... APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9251 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9251 strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD) ...
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... AD9251BCPZRL7-40 –40°C to +85° AD9251BCPZ-20 –40°C to +85° AD9251BCPZRL7-20 –40°C to +85°C 1 AD9251-80EBZ AD9251-65EBZ 1 1 AD9251-40EBZ AD9251-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ...