AD9267 Analog Devices, AD9267 Datasheet
AD9267
Specifications of AD9267
Related parts for AD9267
AD9267 Summary of contents
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... CFILT VIN–B MODULATOR VIN+B AGND The AD9267 operates on a 1.8 V power supply, consuming 416 mW. The AD9267 is available in a 64-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. Continuous time Σ-Δ architecture efficiently achieves high dynamic range and wide bandwidth ...
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... AD9267 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 REVISION HISTORY 7/09—Revision 0: Initial Version ...
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... Full 150.7 Full 151.2 Full 57 Full 8 Full 71.5 Full 0.26 Full 416 Full 503 25°C 110 25°C 9 Full 3 Rev Page AD9267 Max Unit Bits MHz ±0.2 % FSR ±2.5 % FSR LSB ±0.2 % FSR ±1.2 % FSR ppm/°C ppm/°C 505 mV V p-p diff kΩ 1 ...
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... See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 3 Spurious-free dynamic range excluding the second or third harmonic is limited by the FFT size, <−120 dBFS. 4 Noise figure with respect to 50 Ω. AD9267 internal impedance is 1000 Ω differential. See the AN-835 for a definition −2.0 dBFS, unless otherwise noted. Temp ...
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... Full 2 Full 1.2 Full 0 Full −10 Full +40 Full 26 Full 5 LVDS Full 247 Full 1.125 Twos complement LVDS Full 150 Full 1.10 Twos complement Rev Page AD9267 Max Unit 2 V p-p mV +60 μA +60 μA kΩ diff pF DRVDD + 0.3 V 0.8 V −75 μA +10 μA kΩ pF DRVDD + 0.3 V 0.8 V +10 μ ...
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... AD9267 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table 4. 1 Parameter CLOCK INPUT PARAMETERS Input CLK Rate CLK± Period CLK± Duty Cycle CLOCK INPUT PARAMETERS Conversion Rate CLK± Period CLK± Duty Cycle DATA OUTPUT PARAMETERS 2 Data Propagation Delay (t ...
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... V to +3.9 V Package Type −0 +2.5 V 64-Lead LFCSP (CP-64-4) −0 +2.0 V −65°C to +125°C ESD CAUTION −40°C to +85°C 300°C 150°C Rev Page and θ are specified for a 4-layer board in still air θ 22 AD9267 . In JA Unit JA °C/W ...
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... AVDD 53, 54 VIN+A, VIN−A 56 VREF 57 CFILT 59, 60 VIN+B, VIN−B 63 CGND 64 CLK+ 65 Exposed paddle (EPAD) CLK– 1 PIN 1 INDICATOR AD9267 TOP VIEW D0–B 9 (Not to Scale) D0+B 10 D1–B 11 D1+B 12 D2–B 13 D2+B 14 D3–B 15 D3+B 16 Figure 3. Pin Configuration Description Differential Clock Input (− ...
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... All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, T otherwise noted. The output spectrums shown in Figure 4 through Figure 9 were obtained after 16× decimation at the output of the AD9267 and are shown for a 10 MHz bandwidth. ...
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... AD9267 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 50 100 150 200 FREQUENCY (MHz) Figure 10. Noise Transfer Function (NTF) 120 SFDR 100 (dBFS) 80 SNR (dBFS) SFDR 60 (dBc –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 11. Single-Tone SNR and SFDR vs. Input Amplitude with f ...
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... Rev Page 2.4MHz 8.4MHz 5.0 7.0 8.0 9.0 10.5 12.5 15.0 4.5 6.0 7.5 8.5 10.0 12.0 14.0 16.0 PLL DIVIDE RATIO Figure 18. Single-Tone SNR vs. PLL Divide Ratio with f = 2.4 MHz 8.4 MHz IN1 IN2 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 OUTPUT CODE Figure 19. INL with f = 2.4 MHz IN AD9267 17.0 21.0 ...
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... AD9267 EQUIVALENT CIRCUITS 500Ω 2V p-p DIFFERENTIAL 1.8V CM 500Ω Figure 20. Equivalent Analog Input Circuit CVDD CLK+ 10kΩ 10kΩ 90kΩ 30kΩ CVDD Figure 21. Equivalent Clock Input Circuit DRVDD 1kΩ SDIO Figure 22. Equivalent SDIO Input Circuit CLK– Rev Page 1kΩ ...
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... Figure 29. Noise Shaping ANALOG INPUT CONSIDERATIONS The continuous time modulator removes the need for an anti- alias filter at the input to the AD9267. A discrete time converter aliases signals around the sample clock frequency and its multiples to the band of interest (see Figure 30). An external antialias filter is needed to reject these signals ...
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... AD9267 AVDD CLOCK INPUT CONSIDERATIONS The AD9267 offers two modes of sourcing the ADC sample clock (CLK+ and CLK−). The first mode uses an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency. The on-chip phase-locked loop (PLL) then multiplies the reference clock higher frequency, which is then used to generate all the internal clocks required by the Σ ...
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... SCHOTTKY DIODES: 0.1µF HSM2812 Figure 38. Transformer-Coupled Differential Clock If a differential clock is not available, the AD9267 can be driven by a single-ended signal into the CLK+ terminal with the CLK− terminal ac-coupled to ground. Figure 39 shows the circuit configuration. CLOCK INPUT Another option couple a differential LVPECL signal to the sample clock input pins, as shown in Figure 40 ...
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... MHz with a 50% duty cycle. MOD The PLL of the AD9267 can be controlled through either the serial port interface or the PLLMULTx pins. For serial port interface control, Register 0x09 and Register 0x0A are used. Before the PLL enable register bit (PLLENABLE) is set, the PLL multiplica- tion factor should be programmed into Register 0x0A[5:0] ...
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... The OR±x pins are synchronous outputs that are updated at the output data rate. The pins indicate whether an overrange condi- tion has occurred within the AD9267. Ideally, OR±x should be latched on the falling edge of DCO± to ensure proper setup-and- hold time. However, because an overrange condition typically ...
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... OR±x remains high or if the loop filter becomes saturated. The OR±x pin remains high until the automatic reset has completed. If the AD9267 is used in a system that incorporates automatic gain control (AGC), the OR±x signals can be used to indicate that the signal amplitude should be reduced. This may be ...
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... SERIAL PORT INTERFACE (SPI) The AD9267 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 13 comprise the physical interface between the programming device of the user and the serial port of the AD9267. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... FREQUENCY (MHz) Figure 43. STF Figure 43 shows the gain profile of the AD9267 and this can be interpreted as the level in which the signal power should be scaled back to prevent an overload condition. This is the ultimate trip point and before this point is reached, the in-band noise (IBN) slowly degrades result recommended that ...
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... AD9267 Referring to Figure 46, the 3 dB cutoff frequency of the low- pass Chebyshev II filter response resides at 15.75 MHz, and at 10 MHz, there is 0. attenuation due to the sharp roll-off of the filter. Table 15 summarizes the components and manufacturers used to build the circuit. Table 15. Chebyshev II Filter Components ...
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... MSB-first format 1: serial interface uses LSB-first format [5], [ default all serial registers except 0x00, 0x09, and 0x0A [7:0] 0x22 0x22: AD9267 5:4] 0 0x00: 10 MHz bandwidth 0x10: 5 MHz bandwidth 0x20: 2.5 MHz bandwidth 0x30: modulator only [1:0] 0 0x1: Channel A only addressed ...
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... MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9267BCPZ −40°C to +85°C 1 AD9267EBZ RoHs Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 9.00 BSC SQ 0.60 MAX 48 0.50 8.75 TOP VIEW BSC BSC SQ 0 ...