AD7148 Analog Devices, AD7148 Datasheet

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... The AD7148 has an I C®-compatible serial interface, as well as an interrupt output. There for the serial interface independent of V The AD7148 is available in a 16-lead × LFCSP and operates from a 2 3.6 V supply. The operating current consumption in low power mode is typically 26 μ Technology Way, P ...

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... Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Typical Average Current in Low Power Mode ......................... 4 Maximum Average Current in Low Power Mode .................... Timing Specifications (AD7148-1) ..................................... 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 10 Capacitance Sensing Theory ..................................................... 10 BIAS Pin ...

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... V 0 15.5 21.5 μA 2.3 7.5 μA Rev Page AD7148 Test Conditions/Comments 8 conversion stages in sequencer; decimation rate = 256 Guaranteed by design, not production tested Decimation rate = 128 Decimation rate = 256 Decimation rate = 128 Decimation rate = 256 6-bit DAC % of 200 ms, 400 ms, 600 ms, or 800 ms Oscillating Capacitance load on AC ...

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... AD7148 TYPICAL AVERAGE CURRENT IN LOW POWER MODE 25°C, load of 50 pF, unless otherwise noted. CC Table 2. Low Power Mode Delay Decimation Rate 200 ms 64 128 256 400 ms 64 128 256 600 ms 64 128 256 800 ms 64 128 256 MAXIMUM AVERAGE CURRENT IN LOW POWER MODE ...

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... I C TIMING SPECIFICATIONS (AD7148- −40°C to +85° DRIVE All input signals timed from a voltage level of 1.6 V. Table 4. 1 Parameter Limit f 400 SCLK 100 4 t 300 300 R t 300 F 1 Guaranteed by design, not production tested. ...

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... AD7148 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter V to GND CC Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND 1 Input Current to Any Pin Except Supplies ESD Rating (Human Body Model) Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP Power Dissipation θ ...

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... TOP VIEW 10 SDA (Not to Scale) V CIN7 4 9 DRIVE NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINT AND MAXIMUM THERMAL CAPABILITY RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 4. Pin Configuration Rev Page AD7148 ...

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... AD7148 TYPICAL PERFORMANCE CHARACTERISTICS 935 915 895 DECIMATION = 64 875 DECIMATION = 128 855 835 815 795 2.6 2.7 2.8 2.9 3.0 3.1 3.2 V (V) CC Figure 5. Supply Current vs. Supply Voltage 180 200ms 160 140 120 100 400ms 80 600ms 60 800ms 2.5 2.7 2.9 3.1 V (V) CC Figure 6. Low Power Supply Current vs. Supply Voltage, Decimation Rate = 256 ...

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... Figure 14. Power Supply Sine Wave Rejection, V SHIELD 100 120 3.6V 2.6V 95 115 135 Rev Page AD7148 25mV 75mV 125mV 175mV 50mV 100mV 150mV 200mV SINE WAVE FREQUENCY (Hz 10000 20000 30000 40000 50000 60000 CDC OUTPUT CODE Figure 15. CDC Linearity ...

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... The AD7148 has an interrupt output, INT , to indicate when new data has been placed into the registers. INT is used to interrupt the host on sensor activation. The AD7148 operates from a 2 3.6 V supply and is available in a 16-lead × LFCSP. CAPACITANCE SENSING THEORY The AD7148 measures capacitance changes from sensors where one plate is connected to ground ...

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... AD7148 processes the sensor data sensor is touched, the AD7148 measures the ambient capacitance level and uses this data for the on-chip compensation routines. In full power mode, the AD7148 converts at a constant rate. See the CDC Conversion Sequence Time section for more information. Rev Page ...

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... AD7148 transitions to the reduced power state after the user stops touching the sensors. Low Latency from Touch to Response In low power mode, the AD7148 remains in a low power state until proximity is detected on any one of the external sensors. When proximity is detected, the AD718 is automatically configured into the full power mode operation, thus converting each sequence every 36 ms ...

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... The decimation process on the AD7148 is an averaging process, during which a number of samples are taken, and the averaged result is output. Due to the architecture of the digital filter used, the number of samples taken (per stage) is equal to 3× the decima- tion rate. That is, 3 × 256 samples or 3 × 128 samples are averaged to obtain each stage result ...

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... CIN7 Figure 21. CDC Conversion Stages The number of required conversion stages depends completely on the number of sensors attached to the AD7148. Figure 22 shows how many conversion stages are required for each sensor and how many inputs to the AD7148 each sensor requires. A button sensor generally requires one sequencer stage; however possible to configure two button sensors to operate differen- tially. Only one button from the pair can be activated at a time ...

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... In addition to the results registers found in the Bank 3 registers, the AD7148 provides the 16-bit CDC output data directly, starting at Address 0x00B of the Bank 1 registers. Reading back the CDC 16-bit conversion data register allows for customer-specific appli- cation data processing ...

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... The CINx_CONNECTION_SETUP register bits provide options for connecting the sensor input pins to the CDC (see Table 39 and Table 40). The AD7148 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. Each input pin can be tied to either the negative or the positive input of the CDC can be left floating ...

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... This feature provides the ability to detect when a user is approaching a sensor, at which time all internal calibration is immediately disabled while the AD7148 is automatically configured to detect a valid contact. The proximity control register bits are described in Table 12. The ...

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... This means that the ambient value stored on the AD7148 no longer represents the actual ambient value. In this case, even when the user has left the sensor, the proximity flag may still be set. This situation could occur if user interaction creates some moisture on the sensor, causing the new sensor ambient value to be different from the expected value ...

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... Figure 29. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40 USER LEAVES SENSOR MEASURED CDC VALUE > STORED AMBIENT AREA HERE BY PROXIMITY_RECAL _LVL CALDIS RECALIBRATION TIME-OUT CALIBRATION DISABLED LP_CONV_DELAY CONV_LP CONV_FP × LP_PROXIMITY_CNT × 4 × LP_PROXIMITY_RECAL CONV_FP Rev Page RECAL 70 CALIBRATION ENABLED RECAL_TIMEOUT AD7148 t CONV_LP ...

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... Determining the FF_SKIP_CNT value is required only once during the initial setup of the capacitance sensor interface. Table 13 shows how FF_SKIP_CNT controls the update rate to the fast FIFO. Recommended value for this setting, when using all eight conversion stages on the AD7148, is FF_SKIP_CNT = 0000 = no samples skipped. COMPARATOR 1 PROXIMITY 1 WORD0 – ...

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... Rev Page AD7148 Decimation = 256 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × ...

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... Capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. The AD7148 achieves optimal and reliable sensor performance by continuously monitoring the CDC ambient levels and correcting for any changes by adjusting the STAGEx_ HIGH_THRESHOLD and STAGEx_LOW_THRESHOLD register values, as described in Equation 1 and Equation 2 ...

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... Figure 33. Typical Sensor Behavior with Calibration Applied on the Data Path SLOW FIFO As shown in Figure 30, there are a number of FIFOs implemented on the AD7148. These FIFOs are located in Bank 3 of the on-chip memory. The slow FIFOs are used by on-chip logic to monitor the ambient capacitance level from each sensor. ...

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... As a result, the AD7148 maintains optimal threshold and sensitivity levels for all types of users, regardless of finger size. The threshold level is always referenced from the ambient level and is defined as the CDC converter output level that must be exceeded for a valid sensor contact ...

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... POS_PEAK_DETECT percentage of the maximum average, only then is the maximum average value updated. Used in Equation 2. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7148 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGEx_OFFSET_LOW_CLAMP value. ...

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... The sensor touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. Configuring the AD7148 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. The second interrupt is required to alert the host processor that the user is no longer contacting the sensor ...

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... Using AC eliminates capacitance-to-ground pick-up, which SHIELD means that the AD7148 can be placed away from the sensors. This allows the AD7148 to be placed on a separate PCB from the sensors, provided that the connections between the sensors and the CINx inputs are correctly shielded, using AC ...

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... I C serial interface bus. It has a single fixed 7-bit device address, Address 0101 110. The AD7148 responds when the master device sends its device address over the bus. The AD7148 cannot initiate data transfers on the bus. 2 Table 15. AD7148 I C Device Address ...

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... REGISTER ADDRESS[A7:A0 ACK ACK ACK AD7148 DEV ACK 26 27 AD7148 DEVICE ADDRESS DEV DEV DEV ...

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... C Write and Readback Operation This arrangement allows the AD7148 to be connected directly to processors whose supply voltage is less than the minimum 2 C serial operating voltage of the AD7148 without the need for external supplies CC level-shifters. The V supplies as low as 1.65 V and as high as V Rev Page ...

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... The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. Connect the printed circuit board thermal pad to GND. Rev Page AD7148 Min Typ Max Unit 0.1 ...

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... AD7148 POWER-UP SEQUENCE When the AD7148 is powered up, the following sequence is recommended when initially developing the AD7148 and host microprocessor serial interface: 1. Turn on the power supplies to the AD7148. 2. Write to the Bank 2 registers at Address 0x080 through Address 0x0BF. These registers are contiguous sequential register write sequence can be applied. ...

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... CIN4 INT 2 CIN5 SCLK AD7148 BUTTON 3 CIN6 SDA 4 V CIN7 DRIVE BUTTON 100nF 0.1μF Figure 45. Typical Application Circuit Rev Page DRIVE V DRIVE V 2.2kΩ DRIVE 2.2kΩ 2 HOST WITH I INTERFACE 2.2kΩ 12 INT 11 SCK 10 SDO 9 V 2.7V TO 3.6V CC 1μF TO 10μF (OPTIONAL) AD7148 C ...

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... These registers automatically update at the end of each conversion sequence. Although these registers are primarily used by the AD7148 internal data processing, they are accessible by the host processor for additional external data processing, if desired. Default values are undefined for Bank 2 registers and Bank 3 registers until after power-up and configuration of the Bank 2 registers ...

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... Interrupt polarity control R active low 1 = active high R/W Excitation source control 0 = enable excitation source to CINx pins 1 = disable excitation source to CINx pins Unused Set to 0 R/W CDC_BIAS CDC bias current control 00 = normal operation 01 = normal operation + 20 normal operation + 35 normal operation + 50% Rev Page AD7148 ...

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... AD7148 Table 18. STAGEx_CAL_EN Register Default Address Data Bit Value Type 0x001 [0] 0 R/W [1] 0 R/W [2] 0 R/W [3] 0 R/W [4] 0 R/W [5] 0 R/W [6] 0 R/W [7] 0 R/W [11:8] 0 R/W [13:12] 0 R/W [15:14] 0 R/W Mnemonic Description STAGE0_CAL_EN STAGE0 calibration enable 0 = disable 1 = enable STAGE1_CAL_EN STAGE1 calibration enable 0 = disable 1 = enable STAGE2_CAL_EN STAGE2 calibration enable 0 = disable 1 = enable STAGE3_CAL_EN ...

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... PROXIMITY_DETECTION_RATE Proximity detection rate; value is multiplied get actual detection rate SLOW_FILTER_UPDATE_LVL Slow filter update level Mnemonic Description FP_PROXIMITY_RECAL Full power mode proximity recalibration time control LP_PROXIMITY_RECAL Low power mode proximity recalibration time control Rev Page AD7148 ...

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... AD7148 Table 22. STAGEx_LOW_INT_EN Register Default Address Data Bit Value Type 0x005 [0] 0 R/W [1] 0 R/W [2] 0 R/W [3] 0 R/W [4] 0 R/W [5] 0 R/W [6] 0 R/W [7] 0 R/W [11:8] 0 [13:12] 0 R/W [15:14] 0 R/W Mnemonic Description STAGE0_LOW_INT_EN STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE1_LOW_INT_EN STAGE1 low interrupt enable ...

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... INT asserted if STAGE5 high threshold is exceeded STAGE6_HIGH_INT_EN STAGE6 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE6 high threshold is exceeded STAGE7_HIGH_INT_EN STAGE7 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE7 high threshold is exceeded Unused Set unused register bits to 0 Rev Page AD7148 ...

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... AD7148 Table 24. STAGEx_COMPLETE_INT_EN Register Data Default Address Bit Value Type 0x007 [0] 0 R/W [1] 0 R/W [2] 0 R/W [3] 0 R/W [4] 0 R/W [5] 0 R/W [6] 0 R/W [7] 0 R/W [15:8] Table 25. STAGEx_LOW_LIMIT_INT Register Data Default Address Bit Value Type 0x008 [ [ [ [ [ [ [ [ [15:8] 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded ...

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... STAGE5 conversion complete register interrupt status 1 = indicates STAGE5 conversion completed STAGE6_COMPLETE_INT_STATUS STAGE6 conversion complete register interrupt status 1 = indicates STAGE6 conversion completed STAGE7_COMPLETE_INT_STATUS STAGE7 conversion complete register interrupt status 1 = indicates STAGE7 conversion completed Unused Set unused register bits to 0 Rev Page AD7148 ...

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... STAGE6 CDC 16-bit conversion data CDC_RESULT_S7 STAGE7 CDC 16-bit conversion data Mnemonic Description REVISION_CODE AD7148 revision code DEVID AD7148 device ID = 0x148 Mnemonic Description STAGE0_PROXIMITY_STATUS STAGE0 proximity status register 1 = indicates proximity has been detected on STAGE0 STAGE1_PROXIMITY_STATUS STAGE1 proximity status register 1 = indicates proximity has been detected on STAGE1 ...

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... STAGE2_AFE_OFFSET STAGE2 AFE offset control (see Table 41) STAGE2_SENSITIVITY STAGE2 sensitivity control (see Table 42) STAGE2_OFFSET_LOW STAGE2 initial offset low value STAGE2_OFFSET_HIGH STAGE2 initial offset high value STAGE2_OFFSET_HIGH_CLAMP STAGE2 offset high clamp value STAGE2_OFFSET_LOW_CLAMP STAGE2 offset low clamp value Rev Page AD7148 ...

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... AD7148 Table 34. STAGE3 Configuration Registers Data Default Address Bit Value Type 0x098 [15:0] X R/W 0x099 [15:0] X R/W 0x09A [15:0] X R/W 0x09B [15:0] X R/W 0x09C [15:0] X R/W 0x09D [15:0] X R/W 0x09E [15:0] X R/W 0x09F [15:0] X R/W Table 35. STAGE4 Configuration Registers Data Default Address Bit Value Type 0x0A0 [15:0] X R/W 0x0A1 [15:0] X R/W 0x0A2 [15:0] X R/W 0x0A3 [15:0] X R/W 0x0A4 [15:0] X R/W 0x0A5 [15:0] X R/W 0x0A6 [15:0] X R/W 0x0A7 [15:0] X R/W Table 36. STAGE5 Configuration Registers ...

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... CIN5 connected to BIAS (connect unused CINx inputs) CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CINx inputs) Set unused register bits to 0 Rev Page AD7148 ...

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... AD7148 Table 40. STAGEx Detailed CIN7 Connection Setup Description ( Data Default Bit Value Type Mnemonic [1:0] X R/W CIN7_CONNECTION_SETUP [12:2] X Unused [13:12] X R/W SE_CONNECTION_SETUP [14] X R/W NEG_AFE_OFFSET_DISABLE [15] X R/W POS_AFE_OFFSET_DISABLE Table 41. STAGEx Detailed Offset Control Description ( Data Default Bit Value Type Mnemonic [5:0] X R/W NEG_AFE_OFFSET [6] X Unused [7] X NEG_AFE_OFFSET_SWAP ...

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... Positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.48%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level Set to 0 Rev Page AD7148 ...

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... AD7148 BANK 3 REGISTERS All address values are expressed in hexadecimal format. Table 43. STAGE0 Results Registers Data Default Bit Value Address Type 0x0E0 [15:0] X R/W 0x0E1 [15:0] X R/W 0x0E2 [15:0] X R/W 0x0E3 [15:0] X R/W R/W 0x0E4 [15:0] X R/W 0x0E5 [15:0] X 0x0E6 [15:0] X R/W 0x0E7 [15:0] X R/W 0x0E8 [15:0] X R/W 0x0E9 [15:0] X R/W 0x0EA [15:0] X R/W 0x0EB [15:0] X R/W R/W 0x0EC [15:0] X R/W 0x0ED [15:0] X 0x0EE [15:0] X R/W 0x0EF [15:0] X R/W 0x0F0 [15:0] X R/W 0x0F1 [15:0] X R/W 0x0F2 [15:0] X R/W 0x0F3 [15:0] X R/W R/W 0x0F4 ...

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... STAGE1 minimum value FIFO WORD1 STAGE1_MIN_WORD2 STAGE1 minimum value FIFO WORD2 STAGE1_MIN_WORD3 STAGE1 minimum value FIFO WORD3 STAGE1_MIN_AVG STAGE1 average minimum FIFO value STAGE1_LOW_THRESHOLD STAGE1 low threshold value STAGE1_MIN_TEMP STAGE1 temporary minimum value Unused Set unused register bits to 0 Rev Page AD7148 ...

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... AD7148 Table 45. STAGE2 Results Registers Data Default Address Bit Value Type R/W 0x128 [15:0] X R/W 0x129 [15:0] X 0x12A [15:0] X R/W 0x12B [15:0] X R/W 0x12C [15:0] X R/W 0x12D [15:0] X R/W 0x12E [15:0] X R/W 0x12F [15:0] X R/W R/W 0x130 [15:0] X R/W 0x131 [15:0] X 0x132 [15:0] X R/W 0x133 [15:0] X R/W 0x134 [15:0] X R/W 0x135 [15:0] X R/W 0x136 [15:0] X R/W 0x137 [15:0] X R/W R/W 0x138 [15:0] X R/W 0x139 [15:0] X 0x13A [15:0] X R/W 0x13B [15:0] X R/W 0x13C [15:0] X R/W 0x13D [15:0] X R/W 0x13E [15:0] X R/W R/W 0x13F [15:0] X R/W 0x140 [15:0] X 0x141 [15:0] X R/W 0x142 [15:0] X R/W 0x143 [15:0] X R/W 0x144 [15:0] X R/W 0x145 ...

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... STAGE3 minimum value FIFO WORD1 STAGE3_MIN_WORD2 STAGE3 minimum value FIFO WORD2 STAGE3_MIN_WORD3 STAGE3 minimum value FIFO WORD3 STAGE3_MIN_AVG STAGE3 average minimum FIFO value STAGE3_LOW_THRESHOLD STAGE3 low threshold value STAGE3_MIN_TEMP STAGE3 temporary minimum value Unused Set unused register bits to 0 Rev Page AD7148 ...

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... AD7148 Table 47. STAGE4 Results Registers Data Default Address Bit Value Type R/W 0x170 [15:0] X R/W 0x171 [15:0] X 0x172 [15:0] X R/W 0x173 [15:0] X R/W 0x174 [15:0] X R/W 0x175 [15:0] X R/W 0x176 [15:0] X R/W 0x177 [15:0] X R/W R/W 0x178 [15:0] X R/W 0x179 [15:0] X 0x17A [15:0] X R/W 0x17B [15:0] X R/W 0x17C [15:0] X R/W 0x17D [15:0] X R/W 0x17E [15:0] X R/W 0x17F [15:0] X R/W R/W 0x180 [15:0] X R/W 0x181 [15:0] X 0x182 [15:0] X R/W 0x183 [15:0] X R/W 0x184 [15:0] X R/W R/W 0x185 [15:0] X R/W 0x186 [15:0] X 0x187 [15:0] X R/W 0x188 [15:0] X R/W 0x189 [15:0] X R/W 0x18A [15:0] X R/W 0x18B [15:0] X R/W 0x18C [15:0] X R/W R/W 0x18D ...

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... STAGE5 minimum value FIFO WORD1 STAGE5_MIN_WORD2 STAGE5 minimum value FIFO WORD2 STAGE5_MIN_WORD3 STAGE5 minimum value FIFO WORD3 STAGE5_MIN_AVG STAGE5 average minimum FIFO value STAGE5_LOW_THRESHOLD STAGE5 low threshold value STAGE5_MIN_TEMP STAGE5 temporary minimum value Unused Set unused register bits to 0 Rev Page AD7148 ...

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... AD7148 Table 49. STAGE6 Results Registers Data Default Address Bit Value Type R/W 0x1B8 [15:0] X R/W 0x1B9 [15:0] X 0x1BA [15:0] X R/W 0x1BB [15:0] X R/W 0x1BC [15:0] X R/W 0x1BD [15:0] X R/W 0x1BE [15:0] X R/W 0x1BF [15:0] X R/W R/W 0x1C0 [15:0] X R/W 0x1C1 [15:0] X 0x1C2 [15:0] X R/W 0x1C3 [15:0] X R/W 0x1C4 [15:0] X R/W 0x1C5 [15:0] X R/W 0x1C6 [15:0] X R/W 0x1C7 [15:0] X R/W R/W 0x1C8 [15:0] X R/W 0x1C9 [15:0] X 0x1CA [15:0] X R/W 0x1CB [15:0] X R/W 0x1CC [15:0] X R/W 0x1CD [15:0] X R/W 0x1CE [15:0] X R/W 0x1CF [15:0] X R/W R/W 0x1D0 [15:0] X R/W 0x1D1 [15:0] X R/W 0x1D2 [15:0] X 0x1D3 [15:0] X R/W 0x1D4 [15:0] X R/W 0x1D5 ...

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... STAGE7 minimum value FIFO WORD1 STAGE7_MIN_WORD2 STAGE7 minimum value FIFO WORD2 STAGE7_MIN_WORD3 STAGE7 minimum value FIFO WORD3 STAGE7_MIN_AVG STAGE7 average minimum FIFO value STAGE7_LOW_THRESHOLD STAGE7 low threshold value STAGE7_MIN_TEMP STAGE7 temporary minimum value Unused Set unused register bits to 0 Rev Page AD7148 ...

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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD7148ACPZ-1REEL –40°C to +85°C AD7148ACPZ-1500RL7 –40°C to +85° RoHS Compliant Part. ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 4.00 0.60 MAX BSC SQ ...