AD9600 Analog Devices, AD9600 Datasheet
AD9600
Specifications of AD9600
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AD9600 Summary of contents
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... Signal monitor block with dedicated serial output mode. 4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. 5. The AD9600 operates from a single 1.8 V supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families standard serial port interface supports various product ...
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... AD9600 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 AC Specifications .......................................................................... 6 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 9 Timing Characteristics .............................................................. 10 Timing Diagrams ........................................................................ 10 Absolute Maximum Ratings .......................................................... 12 Thermal Characteristics ............................................................ 12 ESD Caution ................................................................................ 12 Pin Configuration and Function Descriptions ........................... 13 Equivalent Circuits ......................................................................... 17 Typical Performance Characteristics ...
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... Changes to Figure 3 ......................................................................... 10 Changes to Figure 11, Figure 12, and Figure 14 .......................... 16 Changes to Table 12 ........................................................................ 28 Changes to Configuration Using the SPI Section ....................... 37 Changes to Table 22 ........................................................................ 40 Changes to Signal Monitor Period (Register 0x113 to Register 0x115) Section .................................................................. 45 Added Exposed Pad Notation to Outline Dimensions .............. 70 11/07—Revision 0: Initial Version Rev Page AD9600 ...
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... AD9600 GENERAL DESCRIPTION The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ...
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... Full 34 365 Full 35 Full 15 42 Full 600 650 Full 645 Full 740 Full 68 Full 2.5 6 Rev Page AD9600ABCPZ-150/ AD9600BCPZ-150 Typ Max Min Typ Max 10 Guaranteed Guaranteed ±0.3 ±0.7 ±0.3 ±0.7 −2.5 −1.3 −4.3 −3.0 −1.6 ±0.2 ±0.2 ±0.1 ±0.1 ±0.3 ± ...
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... Full −72.0 25°C −84.0 25°C −83.0 25°C 85.5 25°C 85.0 Full 72.0 72.0 25°C 83.0 25°C 81.0 25°C −92 25°C −88 Full −81 25°C −86 25°C −86 25°C 84 25°C 82 Full 95 25°C 650 Rev Page AD9600ABCPZ-150/ AD9600BCPZ-150 Typ Max Min Typ Max 60.6 60.6 60.6 60.6 60.3 60.6 60.5 60.5 60.4 60.5 60.5 60.5 60.5 60.1 60.5 60.4 60.4 60.3 9.9 9.9 9.9 9.9 9.9 9.9 9.9 9.9 −86.5 −88.5 −85.0 − ...
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... Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1 Full Full Full Full Full Full Rev Page AD9600 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 GND − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 + CMOS 1.2 GND − ...
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... AD9600 Parameter LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 3.3 V) Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage ( μA) OH High Level Output Voltage ( ...
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... Typ 625 20 105 20 10 105 10 9.5 8 2.85 4.75 6.65 2.4 4 4.28 4.75 5.23 3.6 4 1.6 1.6 0.8 0.8 2.2 4.5 6.4 2.2 4.5 3.8 5.0 6.8 3.8 5.0 5.25 4.5 4.25 3.5 2.4 5.2 6.9 2.4 5.2 4.0 5.6 7.3 4.0 5.6 5.25 4.5 4.25 3.5 3.0 3.7 4.4 3.0 3.8 5.2 6.4 7.6 5.0 6 12/12.5 12/12.5 1.0 1.0 0.1 0.1 350 350 2 3 Rev Page AD9600 AD9600ABCPZ-150/ AD9600BCPZ-150 Max Min Typ Max Unit 625 625 MHz 125 20 150 MSPS 125 10 150 MSPS 6.66 ns 5.6 2.0 3.33 4.66 ns 4.4 3.0 3.33 3.66 ns 1.6 ns 0.8 ns 6.4 2.2 4.5 6.4 ns 6.8 3.8 5.0 6.8 ns 3.83 ns 2.83 ns 6.9 2.4 5.2 6.9 ns 7.3 4.0 5.6 7.3 ns 3.83 ns 2.83 ns 4.5 3.0 3.8 4.5 ns 7.4 4.8 5.9 7 Cycles 12/12.5 Cycles 1 ...
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... AD9600 TIMING CHARACTERISTICS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t Setup time between SYNC and the rising edge of CLK+ SSYNC t Hold time between SYNC and the rising edge of CLK+ HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK ...
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... Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode) Rev Page – – – – – – – CLK DATA AD9600 DATA ...
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... AD9600 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN + A/VIN + B, VIN − A/VIN − AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND ...
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... ADC Master Clock True. The ADC clock can be driven using a single-ended CMOS (see Figure 60 and Figure 61 for the recommended connection). Input ADC Master Clock Complement. The ADC clock can be driven using a single- ended CMOS (see Figure 60 and Figure 61 for the recommended connection). Rev Page AD9600 48 SCLK/DFS 47 SDIO/DCS 46 ...
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... AD9600 Pin No. Mnemonic ADC Fast Detect Outputs 29 FD0A 30 FD1A 31 FD2A 32 FD3A 53 FD0B 54 FD1B 55 FD2B 56 FD3B Digital Inputs 52 SYNC Digital Outputs D0A to D9A 16 to 19, 22, 23 62, 63 D0B to D9B 11 DCOA 10 DCOB SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Port 33 SMI SDO/OEB ...
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... ADC Master Clock Complement. The ADC clock can be driven using a single-ended CMOS (see Figure 60 and Figure 61 for the recommended connection). Rev Page SCLK/DFS 47 SDIO/DCS 46 AVDD 45 AVDD 44 VIN + B 43 VIN – RBIAS 41 CML 40 SENSE 39 VREF 38 VIN – VIN + A 36 AVDD 35 SMI SDFS 34 SMI SCLK/PDWN 33 SMI SDO/OEB AD9600 ...
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... AD9600 Pin No. Mnemonic ADC Fast Detect Outputs 54 FD0+ 53 FD0− 56 FD1+ 55 FD1− 59 FD2+ 58 FD2− 61 FD3+ 60 FD3− Digital Inputs 52 SYNC Digital Outputs 9 D0+ 8 D0− 13 D1+ 12 D1− 15 D2+ 14 D2− 17 D3+ 16 D3− 19 D4+ 18 D4− 23 D5+ 22 D5− ...
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... Figure 10. Digital Output DRVDD DVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS Input Circuit CLK– DVDD DRVDD Rev Page AD9600 DVDD 1kΩ SCLK/DFS 26kΩ Figure 12. Equivalent SCLK/DFS Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit DVDD DVDD 26kΩ ...
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... ENOB = 9.7 BITS SFDR = 77.0dBc –40 –60 SECOND HARMONIC THIRD HARMONIC – FREQUENCY (MHz) Figure 20. AD9600-150 Single-Tone FFT with 150MSPS 337MHz @ –1dBFS SNR = 60.2dB (61.2dBFS) –20 ENOB = 9.7 BITS SFDR = 74.0dBc –40 –60 THIRD HARMONIC SECOND HARMONIC –80 0 ...
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... MHz Figure 25. AD9600-125 Single-Tone FFT with –20 –40 –60 –80 –100 –120 2.3 MHz Figure 26. AD9600-125 Single-Tone FFT with –20 –40 –60 –80 –100 –120 30.3 MHz Figure 27. AD9600-125 Single-Tone FFT with f Rev Page 125MSPS 70.1MHz @ –1dBFS SNR = 60 ...
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... IN –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –20 – with IN SFDR +25°C 300 350 400 450 ) and Figure 33. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN Rev Page SFDR +25° SFDR +85°C 70 SNR +25°C 65 SNR +85°C SNR –40° ...
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... IN2 –24 –12 ) with Figure 37. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency ( 150 MSPS S 46.08 61. with Figure 39. AD9600-150 Single-Tone SNR/SFDR vs. Clock Frequency ( 150 MSPS S Rev Page 150MSPS 169.1MHz @ –7dBFS 172.1MHz @ –7dBFS –20 SFDR = 83.1dBc (90.1dBFS) –40 –60 –80 – ...
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... OUTPUT CODE Figure 42. AD9600 DNL with f IN1 0.10 LSB rms Figure 43. AD9600-150 SNR/SFDR vs. Duty Cycle with f 768 896 1024 = 10.3 MHz Figure 44. AD9600-150 SNR/SFDR vs. Input Common-Mode Voltage (V 768 896 1024 = 10.3 MHz Rev Page 100 ...
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... THEORY OF OPERATION The AD9600 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any f ...
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... AD9600 ADC. The output common-mode voltage of the easily set with the CML pin of the AD9600 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to band limit the input signal. 1V p-p 49.9Ω 499Ω R 499Ω AD8138 0.1µF R 523Ω 499Ω ...
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... VREF Programmable Reference 0 VREF Internal Fixed Reference AGND to 0 the internal reference of the AD9600 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 depicts how the internal reference voltage is affected by loading. –0.25 – ...
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... Jitter Considerations section. Figure 56 and Figure 57 show preferred methods for clocking the AD9600 (at clock rates 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer. ...
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... CLK– The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9600. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources ...
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... DRVDD DRVDD LOAD CLK where N is the number of output bits (22 in the case of AD9600 with the fast detect output pins disabled). This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency ...
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... The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9600. These transients can degrade the dynamic performance of the converter. The lowest typical conversion rate of the AD9600 is typically 10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade. ...
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... FAST DETECT OVERVIEW The AD9600 contains circuitry to facilitate fast overrange detec- tion, allowing very flexible external gain control implementations. Each ADC has four fast detect output pins that are used to output information about the current state of the ADC input level ...
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... An overrange at the input would be indicated by this bit 12 clock cycles after it occurred. GAIN SWITCHING The AD9600 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed ...
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... AD9600 Increment Gain (IG) and Decrement Gain (DG) The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper threshold bits, asserting when the input magnitude is greater than the 3-bit value in the coarse upper threshold register (Address 0x105) ...
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... SPI port or output through the SPORT serial port. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, Rev Page AD9600 DOWN IS COUNT = 1? COUNTER LOAD ...
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... AD9600 the value of the accumulator is reset to the first input sample signal power, and the accumulation continues with the subsequent input samples. Figure 68 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP SIGNAL MONITOR DOWN PERIOD REGISTER COUNTER LOAD FROM CLEAR INPUT ...
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... Register 0x10C, Bits [5:2] (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD9600 ADC sample rate in hertz. CLK DC Correction Readback The current dc correction value can be read back in Register 0x10D and Register 0x10E for Channel A and Register 0x10F and Register 0x110 for Channel B ...
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... AD9600. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9600 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath, starting at the ADC block output. The BIST sequence runs for 512 cycles and then stops ...
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... CHANNEL/CHIP SYNCHRONIZATION The AD9600 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful to guarantee synchronized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific period ...
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... AD9600 SERIAL PORT INTERFACE (SPI) The AD9600 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... Analog Devices, Inc., high speed ADCs, including the AD9600, that are accessible via the SPI are included in Table 21. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9600 part-specific features are described in the Memory Map Register Description section. ...
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... Address 0x13), this address location should not be written. Default Values When the AD9600 comes out of a reset, critical registers are loaded with default values. The default values for the registers are given in the memory map registers table (Table 22). ...
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... Open (Global) 0x0D Test Mode Open Open (Local) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID [7:0] (AD9600 = 0x21) (default) Speed grade ID Open Open 00 = 150 MSPS 01 = 125 MSPS 10 = 105 MSPS MSPS Open Open Open Open Open Open Open ...
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... AD9600 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST Enable Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output type strength 0 = CMOS 3 LVDS CMOS or (global) ANSI LVDS 1.8 V CMOS or reduced: LVDS (global) ...
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... Signal Monitor Period [7:0] Signal Monitor Period [15:8] Signal Monitor Period [23:16] Signal Monitor Result Channel A [7:0] Signal Monitor Result Channel A [15:8] Rev Page AD9600 Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments 0x00 In ADC clock cycles ...
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... AD9600 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x118 Signal Monitor Open Open Result Channel A Register 2 (Global) 0x119 Signal Monitor Result Channel B Register 0 (Global) 0x11A Signal Monitor Result Channel B Register 1 (Global) 0x11B Open Open Signal Monitor Result Channel B Register 2 (Global) MEMORY MAP REGISTER DESCRIPTION ...
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... Register 0x10C, Bits [5:2] (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD9600 ADC sample rate in hertz. CLK Bit 1—DC Correction for Signal Path Enable Setting Bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path ...
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... AD9600 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. Although this register defaults to 64 (0x40), the minimum value for this register is 128 (0x80) cycles— ...
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... The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 47. RBIAS The AD9600 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This register sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... Figure 74 to Figure 83). Figure 73 shows the typical bench characterization setup used to evaluate the ac performance of the AD9600 critical that the signal sources used for the analog input and clock have very low phase noise (<<1 ps rms jitter) to realize the optimum performance of the converter ...
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... The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. When the AD9600 input clock divider is used, clock frequencies up to 625 MHz can be input into the evaluation board through Connector S5. ...
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... AD9600 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet ...
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... SCHEMATICS 10KOHM R41 24.9OHM R29 100OHM R127 K 4.12 R126 DNP R36 24.9OHM R35 F Figure 74. Evaluation Board Schematic, Channel A Analog Inputs Rev Page AD9600 06909-301 57.6OHM R5 33OHM 33OHM R43 R47 OHM 57.6OHM 57.6OHM R1 R28 2 2 ...
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... AD9600 10KOHM R53 AMPVDD 24.9OHM 100OHM R129 K 4.12 R128 DNP R68 24.9OHM R134 R135 F Figure 75. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 06909-302 57.6OHM R72 33OHM 33OHM R70 R71 OHM 0 F R69 F 57.6OHM 57.6OHM R52 R51 2 2 ...
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... R85 R82 OHM 0 R8 Figure 76. Evaluation Board Schematic, DUT Clock Input Rev Page TP2 24.9OHM 1 2 R83 DNP R34 F 57.6OHM 57.6OHM R30 AD9600 06909-303 ...
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... AD9600 100OHM R9 49 VS_OUT67_1 50 VS_OUT67_2 51 VS_OUT01_DIV 52 OUT1B 53 OUT1 54 VS_OUT01_DRV 55 OUT0B 56 OUT0 57 VS_REF K 4.12 58 RSET_CLOCK R12 59 GND_REF 60 R VS_PRESCALE 61 VS_PLL_2 K 5.1 62 CP_RSET R11 63 REFINB 64 REFIN 100OHM R75 Figure 77. Evaluation Board Schematic, Optional AD9516 Clock Circuit Rev Page 06909-304 2 PAD VS_OUT89_2 ...
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... R102 2 RES040 10KOHM R100 10KOHM 10KOHM 24.9OHM R87 TP1 RES060 57.6OHM R45 2 Figure 78. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input Rev Page 06909-305 RES0402 2 RES040 10KOHM R107 R109 RES0402 2 RES040 10KOHM R106 R108 AD9600 ...
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... AD9600 RPAK8 22ohm A FD0 FD1 FD2 FD3 4 13 PWR_SDO PWR_SCL PWR_SDFS RES040 OHM 0 R112 D1A D2A 19 D3A 20 DRGND 21 DRVDD 22 D4A 23 D5A 24 DVDD DVDD 25 D6A 26 D7A 27 D8A 28 D9A(MSB) 29 FD0A 30 FD1A 31 FD2A 32 FD3A Figure 79. Evaluation Board Schematic, DUT Rev ...
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... RES040 10KOHM R118 VAL R130 2 RES040 10KOHM R140 Figure 80. Evaluation Board Schematic, Digital Output Interface Rev Page AD9600 06909-307 100OHM R77 ...
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... AD9600 Figure 81. Evaluation Board Schematic, SPI Circuitry Rev Page 06909-308 RES0402 10KOHM R65 ...
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... M 140KOH R13 GND RES060 261OHM A C R16 CR7 2 1 S2A_REC T SJ35 Figure 82. Evaluation Board Schematic, Power Supply Rev Page 78.7KOH R14 1 TP25 AD9600 06909-309 ...
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... AD9600 4 SJ36 GND 4 1 GND 1 SJ37 M 140KOH R25 GND 4 1 Figure 83. Evaluation Board Schematic, Power Supply (Continued) Rev Page 06909-310 M 78.7KOH R15 ...
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... EVALUATION BOARD LAYOUTS Figure 84. Evaluation Board Layout, Primary Side Rev Page AD9600 ...
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... AD9600 Figure 85. Evaluation Board Layout, Ground Plane Rev Page ...
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... Figure 86. Evaluation Board Layout, Power Plane Rev Page AD9600 ...
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... AD9600 Figure 87. Evaluation Board Layout, Power Plane Rev Page ...
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... Figure 88. Evaluation Board Layout, Ground Plane Rev Page AD9600 ...
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... AD9600 Figure 89. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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... Figure 90. Evaluation Board Layout, Silkscreen, Primary Side Rev Page AD9600 ...
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... AD9600 Figure 91. Evaluation Board Layout, Silk Screen, Secondary Side Rev Page ...
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... Panasonic PTMICRO6 Weiland Electric, Inc. PTMICRO4 Weiland Electric, Inc. R0603 NIC Components R0402SM NIC Components R0603 NIC Components R0603 NIC Components Rev Page AD9600 Mfg. Part Number GRM155R71C104KA88D GJM1555C1H180JB01J GJM1555C1H4R7CB01J GRM155R71H102KA01D GR4M219R61A105KC01D GRM31CR61C106KC31L HSMS-2822-BLKG LNJ208R8ARA S2A-TP SK33-TP BNX016-01 NANOSMDC150F-2 TWS-1003-08-G-S ...
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... W, 1% resistor 34 4 S2, S3, S5 ,S12 SMA, inline, male, coaxial connector 35 1 SJ35 0 Ω, 1 resistor Balun IC, AD9600 Clock distribution, PLL Dual inverter Dual buffer IC, open-drain circuits UHS dual buffer IC ...
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... THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.60 MAX PIN 1 INDICATOR 64 1 7.65 EXPOSED PAD 7.50 SQ (BOTTOM VIEW) 7. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD9600 ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board with AD9600 and Software D06909-0-12/09(B) Rev Page Package Option CP-64-6 ...