AD9601 Analog Devices, AD9601 Datasheet
AD9601
Specifications of AD9601
Related parts for AD9601
AD9601 Summary of contents
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... CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9601 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). ...
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... Digital Outputs ........................................................................... 18 Timing—Single Port Mode ....................................................... 19 Timing—Interleaved Mode....................................................... 19 Layout Considerations................................................................... 20 Power and Ground Recommendations ................................... 20 CML ............................................................................................. 20 RBIAS........................................................................................... 20 AD9601 Configuration Using the SPI ..................................... 20 Hardware Interface..................................................................... 21 Configuration Without the SPI ................................................ 21 Memory Map .................................................................................. 23 Reading the Memory Map Table.............................................. 23 Reserved Locations .................................................................... 23 Default Values ............................................................................. 23 Logic Levels................................................................................. 23 Evaluation Board ...
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... MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9601. 5 Interleaved mode; user-programmable feature. See the Memory Map section. = +85° −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled, ...
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... AD9601-200 Temp Min Typ 25°C 59.5 Full 25°C 59.3 25°C 59.5 Full 25°C 59.3 25°C 9.6 25°C 9.6 25°C 84 Full 25°C 78 25°C 88 Full 25°C 87 25°C 81 25°C 700 Rev Page AD9601-250 Max Min Typ Max 59.4 58.5 57.8 59.4 59.4 58.5 57.7 59.4 9.7 9 700 1 Unit ...
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... VDD Full 0.2 × AVDD Full 0 Full −60 Full 55 Full 0 25°C 4 Full DRVDD − 0.05 Full GND + 0.05 Twos complement, Gray code, or offset binary (default) Rev Page AD9601 AD9601-250 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3 0.8 × VDD 0.2 × ...
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... Full 200 Full 40 Full 2.15 2.4 Full 2.15 2.4 25°C 3.7 25°C 3.4 Full 0 0.3 0.55 Full 6 25°C 3.5 25°C 3.0 Full 0 0.5 1.1 Full 6 25°C 250 50 25°C 0.1 25°C 0.2 Rev Page AD9601-250 Min Typ Max Unit 250 MSPS 40 MSPS 1.8 2.0 ns 1.8 2.0 ns 3 0.3 0. Cycles 3 0.5 1 Cycles 250 ns 50 μs ...
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... CLK t t CPDA CPDB t SKEWA N – – – SKEWB t PDB N – – 3 Figure 3. Interleaved Mode Rev Page – – AD9601 ...
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... AD9601 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD Dx0 Through Dx9 to DRGND DCO+/DCO− to DRGND OVRA/OVRB to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND SDIO/DCS to DGND PDWN to AGND CSB to AGND ...
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... Output Port A Output Bit 0 (LSB). Output Port A Output Bit 1. Output Port A Output Bit 2. Output Port A Output Bit 3. Output Port A Output Bit 4. Output Port A Output Bit 5. Output Port A Output Bit 6. Rev Page AD9601 42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– ...
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... AD9601 Pin No. Mnemonic 4 DA7 5 DA8 6 DA9 (MSB) 10, 11, 51, 52 NIC 9 OVRA 12 DB0 (LSB) 13 DB1 14 DB2 15 DB3 16 DB4 17 DB5 18 DB6 19 DB7 20 DB8 21 DB9 (MSB) 22 OVRB 1 AGND and DRGND should be tied to a common quiet ground plane. Description Output Port A Output Bit 7. Output Port A Output Bit 8. ...
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... Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit CLK– AVDD V CML ~1.4V = ~1.4 V) Rev Page AVDD 26kΩ 1kΩ CSB Figure 8. Equivalent CSB Input Circuit DRVDD DRGND Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−) DRVDD 1kΩ SDIO/DCS Figure 10. Equivalent SDIO/DCS Input Circuit AD9601 ...
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... SNR: 59.3dB ENOB: 9.7 BITS SFDR: 78dBc –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 12. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 13. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 170.3 MHz = 25° ...
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... Figure 20. SNR/SFDR vs. Analog Input Frequency, Interleaved Mode vs. 0 –20 –40 –60 –80 –100 –120 –140 245 0 Figure 21. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz 0 250MSPS 70.3MHz @ –1.0dBFS –20 SNR: 59.4dB ENOB: 9.7 BITS SFDR: 81dBc –40 –60 –80 –100 –120 – ...
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... ANALOG INPUT FREQUENCY (MHz) Figure 25. AD9601-250 Single-Tone SNR/SFDR vs. Input Frequency (f Temperature with 1.25 V p-p Full Scale; 250 MSPS 80 100 120 Figure 26. AD9601-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz 350 400 450 500 ) and IN Rev Page ...
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... OUTPUT CODE Figure 29. AD9601-250 DNL; 250 MSPS 90 SFDR SNR 125 175 225 SAMPLE RATE (MSPS) Figure 30. SNR/SFDR vs. Sample Rate; AD9626-250 , 170.3 MHz @ −1 dBFS 2.5 2.0 1.5 1.0 0.5 0 –0.5 768 896 – ...
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... During power- down, the output buffers go into a high impedance state. ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9601 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical ...
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... This allows a wide range of clock input duty cycles without affecting the performance of the AD9601. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS 0.1µ ...
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... ANALOG INPUT FREQUENCY (MHz) Figure 41. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS Input Signal POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 28, the power dissipated by the AD9601 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers ...
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... Depending on the relationship of the IF frequency to the center of the Nyquist zone, this spurious tone may or may not be in the user’s band of interest. Some residual f the AD9601, and the level of this spur is typically below the level of the harmonics at clock rates. Figure 20 shows a plot of the f /2 spur level vs ...
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... The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 45. RBIAS The AD9601 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... The pins described in Table 8 comprise the physical interface between the user’s programming device and the serial port of the AD9601. All serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 kΩ). ...
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... AD9601 Table 10. Serial Timing Definitions Parameter Timing (minimum, ns CLK EN_SDIO t 5 DIS_SDIO Table 11. Output Data Format Input (V) Condition (V) VIN+ − VIN− < 0.62 VIN+ − VIN− = 0.62 VIN+ − VIN− ...
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... Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID, Bits[7:0] AD9601 = 0x36 0 Speed grade 200 MSPS 10 = 250 MSPS PDWN: ...
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... AD9601 Addr Bit 7 (Hex) Parameter Name (MSB) Bit 6 09 clock test_io OF ain_config output_mode output_phase Output 0 clock polarity 1 = inverted 0 = normal (default) 17 flex_output_delay Output delay enable enable 1 = disable 18 flex_vref Bit 5 Bit 4 Bit 3 Bit Reset Reset Output test mode: ...
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... CMLX 33 33 optional R16 C21 0.1UF 10K R12 PRI SEC ETC1-1-13 Figure 45. AD9601 Evaluation Board Schematic Page 1 Rev Page 07100-045 GND GND GND DRVDD AVDD AVDD CR2 CR3 1 0.1UF C75 3 2 0.1UF C15 AD9601 ...
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... C56 0.1UF C57 0.1UF C58 OUT 4 C3 1UF R2 OUT 4 499 C1 1UF OUT 4 C7 1UF OUT 1UF Figure 46. AD9601 Evaluation Board Schematic Page 2 Rev Page 07100-046 VCLK GND GND 1 FERRITE VSPIEXTX OUT1 2 VSPIEXTX VIN ...
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... C76 DNP L10 L11 DNP C45 C44 DNP DNP GND E13 E14 E12 DNP DNP C41 C40 R47 R36 00 00 Figure 47. AD9601 Evaluation Board Schematic Page R63 R65 R67 R69 R71 R73 R64 R66 R68 R70 ...
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... R27 SDO_CHA CSB1_CHA SDI_CHA SCLK_CHA Figure 48. AD9601 Evaluation Board Schematic Page 4 Description PCB, AD9230 customer evaluation board, Rev. G Capacitor, 1 μF, 0603, X5R, ceramic, 6.3 V, 10% Capacitor, 10 μF, tantalum 10% Capacitor, 2.0 pF ceramic, 0402, SMD Capacitor, 0.33 μF, ceramic, X5R 10% Capacitor, 120 pF, ceramic, C0G Capacitor, 0.1 μ ...
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... Capacitor, 0.1 μF, ceramic, 10% LED green, USS type 0603 Schottky diode Connector, header, 0.1" TSW-110-08-G-D Connector, PCB coax SMA end launch, Johnson 142 Inductor SMA Rev Page AD9601 Vendor Part Number Panasonic ERJ-2GEJ360X Panasonic ERJ-2RKF15R0X NIC Components NRC04F1001TRF NIC Components ...
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... AD9601 Reference Qty Designator Package 0 R3, R14, R33, 402 R34, R35, R48, R49 0 R42, R43, R54, 402 R85, R86 0 R28, R29, R30, 402 R31, R32 0 R37, R38 402 0 R39, R45 402 0 R58, R59 402 0 R60, R61 402 0 R8, R9, R17, 402 R36, R40, R41, ...
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... Figure 49. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CMOS Evaluation Board with AD9601BCPZ-250 Rev Page 0.30 0.23 0.18 PIN 1 56 ...
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... AD9601 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07100-0-11/07(0) Rev Page ...