AD9259 Analog Devices, AD9259 Datasheet
AD9259
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AD9259 Summary of contents
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... The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI). The AD9259 is available in a RoHS-compliant, 48-lead LFCSP specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1 ...
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... AD9259 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagrams .......................................................................... 8 Absolute Maximum Ratings .......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 13 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 19 Analog Input Considerations ...
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... Changes to Reading the Memory Map Table Section ...................... 30 Change to Output Signals Section ........................................................ 34 Changes to Figure 60 ............................................................................... 34 Changes to Default Operation and Jumper Selection Settings Section ................................................... 35 Changes to Alternative Analog Input Drive Configuration Section ........................................................................ 36 Changes to Figure 63 ............................................................................... 38 Changes to Table 17 ................................................................................. 46 Changes to Ordering Guide ................................................................... 50 6/06—Revision 0: Initial Version Rev Page AD9259 ...
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... AD9259 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error ...
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... Full Full 70.2 Full Full Full 11.5 Full Full Full 73 Full Full Full Full Full Full Full 25°C 25°C www.analog.com for definitions and for details on how these tests were Rev Page AD9259 Typ Max Unit 73.5 dB 73.0 dB 72.8 dB 72.7 dB 72.2 dB 72.0 dB 11.92 Bits 11.85 Bits 11.8 Bits 84 dBc ...
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... AD9259 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage ...
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... SAMPLE SAMPLE Full ±50 25°C 600 25°C 375 Full 8 25°C 500 25°C <1 25°C 2 www.analog.com Rev Page AD9259 Max 10 3.5 3.5 + /28) /28) (t /28) + 300 SAMPLE /28) (t /28) + 300 SAMPLE ±150 for definitions and for details on how these tests were Unit MSPS MSPS ...
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... AD9259 TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – x ...
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... N – – – – 9 Figure 4. 14-Bit Data Serial Stream, LSB First Rev Page D10 D11 D12 N – – – – – – – 9 AD9259 LSB D0 N – – 8 ...
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... AD9259 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD Digital Outputs 1 to DRGND CLK+, CLK− to AGND VIN + x, VIN – AGND SDIO/ODM to AGND PDWN, SCLK/DTP, CSB to AGND REFT, REFB, RBIAS to AGND VREF, SENSE to AGND ...
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... ADC A Digital Output Complement ADC A Digital Output True Frame Clock Output Complement Frame Clock Output True Data Clock Output Complement Data Clock Output True Serial Clock/Digital Test Pattern Serial Data I/O/Output Driver Mode Rev Page AD9259 AVDD 36 AVDD 35 VIN – VIN + A 33 ...
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... AD9259 Pin No. Mnemonic 30 CSB 31 PDWN 33 VIN + A 34 VIN − VIN − VIN + B 40 RBIAS 41 SENSE 42 VREF 43 REFB 44 REFT 47 VIN + C 48 VIN − C Description Chip Select Bar Power-Down ADC A Analog Input True ADC A Analog Input Complement ADC B Analog Input Complement ...
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... Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V AND PDWN Rev Page DRVDD V V D– DRGND Figure 9. Equivalent Digital Output Circuit 1kΩ SCLK/DTP 30kΩ Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit 100Ω RBIAS Figure 11. Equivalent RBIAS Circuit AD9259 ...
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... AD9259 AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page Data Sheet 6kΩ ...
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... AIN = –0.5dBFS SNR = 66.87dB ENOB = 10.82 BITS SFDR = 74.97dBc FREQUENCY (MHz) = 190 MHz SAMPLE 0 AIN = –0.5dBFS SNR = 65.62dB ENOB = 10.61 BITS SFDR = 68.11dBc FREQUENCY (MHz) = 250 MHz SAMPLE AD9259 MSPS MSPS MSPS ...
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... AD9259 90 2V p-p, SFDR p-p, SNR ENCODE (MSPS) Figure 21. SNR/SFDR vs. Encode 10.3 MHz p-p, SFDR p-p, SNR ENCODE (MSPS) Figure 22. SNR/SFDR vs. Encode MHz 100 f = 10.3MHz 50MSPS SAMPLE p-p, SFDR 60 50 ...
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... FREQUENCY (MHz) Figure 31. CMRR vs. Frequency MSPS SAMPLE 1.2 1.006 LSB rms 1.0 0.8 0.6 0.4 0 – – – CODE Figure 32. Input-Referred Noise Histogram, f SAMPLE AD9259 MSPS ...
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... AD9259 0 NPR = 63.89dB NOTCH = 18.0MHz –20 NOTCH WIDTH = 3.0MHz –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 33. Noise Power Ratio (NPR MSPS Figure 34. Full-Power Bandwidth vs. Frequency, f SAMPLE Rev Page –1 –2 –3dB CUTOFF = 315MHz –3 – ...
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... Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information at www.analog.com. In general, the precise values depend on the application. The analog inputs of the AD9259 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that V ...
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... In the case of the AD9259, the largest input span available p-p. Differential Input Configurations There are several ways to drive the AD9259 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the ...
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... This allows a wide range 0.1µF of clock input duty cycles without affecting the performance of CLK+ the AD9259. When the DCS is on, noise and distortion perfor- ADC 100Ω AD9259 mance are nearly flat for a wide range of duty cycles. However, 0.1µ ...
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... ANALOG INPUT FREQUENCY (MHz) Figure 47. Ideal SNR vs. Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 48, the power dissipated by the AD9259 is ) proportional to its sample rate. The digital power dissipation A does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. ...
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... Data Sheet By asserting the PDWN pin high, the AD9259 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI features are changed before the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset ...
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... AD9259 EYE: ALL BITS 500 0 0 –500 –1.0ns –0.5ns 0ns 100 50 0 –100ps 0ps Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only EYE: ALL BITS 200 0 – ...
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... Data Sheet Two output clocks are provided to assist in capturing data from the AD9259. The DCO is used to clock the output data and is equal to seven times the sample clock (CLK) rate. Data is clocked out of the AD9259 and must be captured on the rising and falling edges of the DCO that supports double data rate Table 9 ...
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... Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9259 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence Initial ...
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... ADC to a nominal 185 MSPS. Therefore imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable, accurate 0.5 V voltage reference is built into the AD9259. This is gained up internally by a factor of 2, setting V to 1.0 V, which results in a full-scale differential input span REF p-p. The V VREF pin can be driven externally with a 1 ...
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... The analog input full- scale range of the ADC equals twice the voltage of the reference pin for either an internal or an external reference configuration. If the reference of the AD9259 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 55 depicts how the internal reference voltage is affected by loading ...
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... If multiple SDIO pins share a common connection, care should be taken to ensure that proper V same load for each AD9259, Figure 57 shows the number of SDIO pins that can be connected together and the resulting V level. This interface is flexible enough to be controlled by either ...
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... AD9259 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 57. SDIO Pin Loading CSB SCLK DON’T CARE R A12 SDIO DON’ ...
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... Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9259 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. ...
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... Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset off 0 = off (default) (default) 8-bit Chip ID Bits [7:0] (AD9259 = 0x04), (default Clock Clock Data Data channel channel Channel Channel DCO FCO ...
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... Rev Page AD9259 Default (LSB) Value Default Notes/ Bit 1 Bit 0 (Hex) Comments 00 = offset binary 0x00 Configures the (default) outputs and the 01 = twos format of the complement data ...
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... AD9259. An exposed continuous copper plane on the PCB should mate to the AD9259 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. ...
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... Figure 62 to Figure 66). Figure 60 shows the typical bench characterization setup used to evaluate the ac performance of the AD9259 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter ...
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... AD9259 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9259 Rev. A evaluation board. POWER: Connect the switching power supply that is provided in the evaluation kit between a rated 100 240 V ac wall outlet and P503. ...
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... Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332. In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev Page AD9259 ...
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... AD9259 VGA INPUT CONNECTION INH1 CHANNEL A R101 P101 DNP AIN R102 64.9Ω VGA INPUT CONNECTION CHANNEL B P103 AIN P106 DNP VGA INPUT CONNECTION INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0Ω 64.9Ω AVDD_DUT VGA INPUT CONNECTION INH4 CHANNEL D P107 ...
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... D 19 CHB CHB B – CHC CHC C – VIN CHD – VIN CHD D – Rev Page AD9259 GND RSET S10 32 7 VREF 6 1 ...
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... AD9259 POPULATE L301 TO L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. R312 10kΩ R313 10kΩ DNP C311 0.1µF C312 0.1µF R315 C315 10kΩ 10µF DNP: DO NOT POPULATE Figure 64. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit ...
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... Rev Page J401 PICVCC 1 2 PICVCC GP1 3 4 GP1 GP0 5 6 GP0 MCLR/GP3 7 8 MCLR/GP3 9 10 PIC PROGRAMMING HEADER GAIN NEGATIVE GAIN POSITIVE PIN MODE 0.018µF 274Ω C420 R416 8 AVDD_5V AVDD_5V 2 1 GAIN LO GAIN HI PIN HILO OPTIONAL AD9259 ...
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... AD9259 Figure 66. Evaluation Board Schematic, Power Supply Inputs Rev Page Data Sheet GND GND 1 1 GND GND 1 1 ...
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... Data Sheet Figure 67. Evaluation Board Layout, Primary Side Rev Page AD9259 ...
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... AD9259 Figure 68. Evaluation Board Layout, Ground Plane Rev Page Data Sheet ...
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... Data Sheet Figure 69. Evaluation Board Layout, Power Plane Rev Page AD9259 ...
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... AD9259 Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page Data Sheet ...
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... SOT- mA, dual Schottky LED 603 Green candela Diode DO-214AB SMC Diode DO-214AA SMC Rev Page AD9259 Manufacturer’s Manufacturer Part Number Murata GRM155R71C104KA88D Murata GRM1555C1H2R2GZ01B Murata GRM219R60J106KE19D Murata GRM188C70J225KE20D Murata GRM155R71H102KA01D AVX ...
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... AD9259 Item Qty. Reference Designator 17 1 F501 18 1 FER501 19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 20 1 JP301 21 2 J205, J402 22 4 J201 to J204 23 1 J401 24 8 L501, L502, L503, L504, L505, L506, L507, L508 ...
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... W, 1% tol Switch SMD Light touch, 100GE Transformer CD542 ADT1-1WT, 1:1 impedance ratio transformer IC SOT-223 ADP3339AKC-1.8, 1.5 A, 1.8 V LDO regulator Rev Page AD9259 Manufacturer’s Manufacturer Part Number NIC NRC04F1001TRF Components NIC NRC04J330TRF Components NIC NRC04F4990TRF Components NIC NRC04F1003TRF Components NIC ...
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... RAM size 64 × MHz speed, PIC12F controller series Rev Page Data Sheet Manufacturer’s Manufacturer Part Number Analog Devices AD8332ACPZ Analog Devices ADP3339AKCZ-5 Analog Devices ADP3339AKCZ-3.3 Analog Devices AD9259BCPZ-50 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ Fairchild NC7WZ07P6X_NL Fairchild NC7WZ16P6X_NL Microchip PIC12F629-I/SN ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel Evaluation Board Rev Page 0.30 0.23 0.18 PIN 1 INDICATOR 5.55 EXPOSED 5.50 SQ PAD 5.45 (BOTTOM VIEW 0.22 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD9259 Package Option CP-48-8 CP-48-8 ...
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... AD9259 NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05965-0-1 /11(E) Rev Page Data Sheet ...