AD9287 Analog Devices, AD9287 Datasheet

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AD9287

Manufacturer Part Number
AD9287
Description
Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9287

Resolution (bits)
8bit
# Chan
4
Sample Rate
100MSPS
Interface
LVDS,Ser
Analog Input Type
Diff-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
Data Sheet
FEATURES
4 ADCs integrated into 1 package
133 mW ADC power per channel at 100 MSPS
SNR = 49 dB (to Nyquist)
ENOB = 7.85 bits
SFDR = 65 dBc (to Nyquist)
Excellent linearity
Serial LVDS (ANSI-644, default)
Data and frame clock outputs
295 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 100 MSPS and is optimized
for outstanding dynamic performance and low power in
applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DNL = ±0.2 LSB (typical)
INL = ±0.2 LSB (typical)
Low power, reduced signal option (similar to IEEE 1596.3)
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9287 is available in an RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
SENSE
REFB
VREF
REFT
Small Footprint. Four ADCs are contained in a small, space-
saving package.
Low power of 133 mW/channel at 100 MSPS.
Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 400 MHz and supports
double data rate (DDR) operation.
User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
Pin-Compatible Family. This includes the AD9219 (10-bit),
AD9228 (12-bit), and AD9259 (14-bit).
AVDD
SELECT
REF
RBIAS
FUNCTIONAL BLOCK DIAGRAM
Quad, 8-Bit, 100 MSPS,
AGND
Serial LVDS 1.8 V ADC
+ –
©2006–2011 Analog Devices, Inc. All rights reserved.
AD9287
T/H
T/H
T/H
T/H
0.5V
CSB
PDWN
SERIAL PORT
INTERFACE
SDIO/ODM
Figure 1.
PIPELINE
PIPELINE
PIPELINE
PIPELINE
ADC
ADC
ADC
ADC
SCLK/DTP
DRVDD
8
8
8
8
MULTIPLIER
DATA RATE
CLK+
SERIAL
SERIAL
SERIAL
SERIAL
LVDS
LVDS
LVDS
LVDS
AD9287
www.analog.com
DRGND
CLK–
D + A
D – A
D + B
D – B
D + C
D – C
D + D
D – D
FCO+
FCO–
DCO+
DCO–

Related parts for AD9287

AD9287 Summary of contents

Page 1

... The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI). The AD9287 is available in an RoHS compliant, 48-lead LFCSP specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1 ...

Page 2

... AD9287 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagrams .............................................................................. 8 Absolute Maximum Ratings .......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 13 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 19 Analog Input Considerations ...

Page 3

... Changes to Reading the Memory Map Table Section ................ 30 Changes to Output Signals Section............................................... 34 Changes to Figure 60 ...................................................................... 34 Changes to Default Operation and Jumper Selection Settings Section ................................................ 35 Changes to Alternative Analog Input Drive Configuration Section .................................................................... 36 Changes to Figure 63 ...................................................................... 38 Changes to Table 17 ........................................................................ 46 Changes to Ordering Guide ........................................................... 50 7/06—Revision 0: Initial Version Rev Page AD9287 ...

Page 4

... AD9287 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error ...

Page 5

... Full Full 46.0 Full Full Full 7.43 Full Full Full 54.0 Full Full Full Full Full Full Full 25°C 25°C www.analog.com for definitions and for details on how these tests were Rev Page AD9287 Typ Max Unit 49.2 dB 49.0 dB 49.0 dB 49.0 dB 48.5 dB 48.5 dB 7.88 Bits 7.85 Bits 7.85 Bits 70.0 dBc 65 ...

Page 6

... AD9287 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage ...

Page 7

... Rev Page Max Unit MSPS 10 MSPS /16) /16) (t /16) + 300 ps SAMPLE /16) (t /16) + 300 ps SAMPLE ±150 ps ns μs CLK cycles ps ps rms CLK cycles for definitions and for details on how these tests were AD9287 ...

Page 8

... AD9287 TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – x ...

Page 9

... – – – – – – – 9 Figure 4. 8-Bit Data Serial Stream, LSB First Rev Page AD9287 N D6 LSB – – – – – – – ...

Page 10

... AD9287 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x AGND SDIO/ODM AGND PDWN, SCLK/DTP, CSB ...

Page 11

... Frame Clock Output Complement Frame Clock Output True Data Clock Output Complement Data Clock Output True Serial Clock/Digital Test Pattern Serial Data IO/Output Driver Mode Chip Select Bar Power-Down ADC A Analog Input True Rev Page AD9287 AVDD 36 AVDD 35 VIN – VIN + ...

Page 12

... AD9287 Pin No. Mnemonic 34 VIN − VIN − VIN + B 40 RBIAS 41 SENSE 42 VREF 43 REFB 44 REFT 47 VIN + C 48 VIN − C Description ADC A Analog Input Complement ADC B Analog Input Complement ADC B Analog Input True External resistor sets the internal ADC core bias current ...

Page 13

... Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V SCLK/DTP Rev Page DRVDD V V D– DRGND Figure 9. Equivalent Digital Output Circuit 1kΩ AND PDWN 30kΩ Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit 100Ω RBIAS Figure 11. Equivalent RBIAS Circuit AD9287 ...

Page 14

... AD9287 AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page Data Sheet 6kΩ ...

Page 15

... SFDR = 61.37dBc FREQUENCY (MHz) = 190 MHz SAMPLE AIN = –0.5dBFS SNR = 48.32dB ENOB = 7.73 BITS SFDR = 54.48dBc FREQUENCY (MHz) = 225 MHz SAMPLE AD9287 100 MSPS 100 MSPS 100 MSPS ...

Page 16

... AD9287 p-p, SFDR p-p, SNR (MSPS) SAMPLE Figure 21. SNR/SFDR vs 10.3 MHz, f SAMPLE p-p, SFDR p-p, SNR (MSPS) SAMPLE Figure 22. SNR/SFDR vs MHz, f SAMPLE p-p, SFDR p-p, SNR ...

Page 17

... ANALOG INPUT FREQUENCY (MHz) Figure 31. CMRR vs. Analog Input Frequency, f SAMPLE 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2 (MSPS) SAMPLE Figure 32. Input Full-Scale Amplitude vs. f AD9287 200 250 100 MSPS 80 90 100 SAMPLE ...

Page 18

... AD9287 –10 –30 –50 –70 –90 –110 FREQUENCY (MHz) Figure 33. Noise Power Ratio (NPR), f NPR = 40.12dB NOTCH = 18MHz NOTCH WIDTH = 3MHz 100 MSPS SAMPLE Rev Page –1 –2 –3dB CUTOFF = 295MHz –3 –4 –5 – ...

Page 19

... Wideband A/D Converters” (Volume 39, April 2005) for more information at www.analog.com. In general, the precise values depend on the application. The analog inputs of the AD9287 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that V recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 36 and Figure 37 ...

Page 20

... In the case of the AD9287, the largest input span available p-p. Differential Input Configurations There are several ways to drive the AD9287 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the ...

Page 21

... Schottky diodes across the secondary transformer limit clock excursions into the AD9287 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9287, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. ...

Page 22

... ANALOG INPUT FREQUENCY (MHz) Figure 47. Ideal SNR vs. Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 48, the power dissipated by the AD9287 is ) proportional to its sample rate. The digital power dissipation A does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. ...

Page 23

... Data Sheet By asserting the PDWN pin high, the AD9287 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI features are changed before the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset ...

Page 24

... AD9287 EYE: ALL BITS 500 0 –500 –1.0ns –0.5ns 0ns 100 50 0 –100ps 0ps Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only EYE: ALL BITS 200 0 –200 – ...

Page 25

... Data Sheet Two output clocks are provided to assist in capturing data from the AD9287. The DCO is used to clock the output data and is equal to four times the sample clock (CLK) rate. Data is clocked out of the AD9287 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) Table 9 ...

Page 26

... Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9287 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence Initial ...

Page 27

... ADC to a nominal 260 mA at 100 MSPS. Therefore imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable, accurate 0.5 V voltage reference is built into the AD9287. This is gained up internally by a factor of 2, setting V to 1.0 V, which results in a full-scale differential input span REF p-p. The V VREF pin can be driven externally with a 1 ...

Page 28

... The analog input full- scale range of the ADC equals twice the voltage of the reference pin for either an internal or an external reference configuration. If the reference of the AD9287 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 55 depicts how the internal reference voltage is affected by loading ...

Page 29

... If multiple SDIO pins share a common connection, care should be taken to ensure that proper V same load for each AD9287, Figure 57 shows the number of SDIO pins that can be connected together and the resulting V level. This interface is flexible enough to be controlled by either ...

Page 30

... AD9287 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 57. SDIO Pin Loading CSB SCLK DON’T CARE R A12 SDIO DON’ ...

Page 31

... Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9287 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. ...

Page 32

... Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset off 0 = off (default) (default) 8-bit Chip ID Bits [7:0] (AD9287 = 0x05), (default Clock Clock Data Data Channel Channel Channel Channel DCO FCO ...

Page 33

... Rev Page AD9287 Default (LSB) Value Default Notes/ Bit 1 Bit 0 (Hex) Comments 00 = offset binary 0x00 Configures the (default) outputs and the 01 = twos format of the complement data ...

Page 34

... AD9287. An exposed continuous copper plane on the PCB should mate to the AD9287 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. ...

Page 35

... Figure 62 to Figure 66). Figure 60 shows the typical bench characterization setup used to evaluate the ac performance of the AD9287 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter ...

Page 36

... AD9287 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9287 Rev. A evaluation board. • POWER: Connect the switching power supply that is provided with the evaluation kit between a rated 100 240 V ac wall outlet and P503. ...

Page 37

... Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332. In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev Page AD9287 ...

Page 38

... AD9287 VGA INPUT CONNECTION INH1 CHANNEL A R101 P101 DNP AIN R102 64.9Ω VGA INPUT CONNECTION CHANNEL B P103 AIN P106 DNP VGA INPUT CONNECTION INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0Ω 64.9Ω AVDD_DUT VGA INPUT CONNECTION INH4 CHANNEL D P107 ...

Page 39

... CHB B – AVDD CHC AVDD CHC C – VIN CHD – VIN CHD D – Rev Page AD9287 05966-016 GND RSET S10 32 7 VREF ...

Page 40

... AD9287 POPULATE L301 TO L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. R312 10kΩ R313 10kΩ DNP C311 0.1µF C312 0.1µF R315 C315 10kΩ 10µF DNP: DO NOT POPULATE Figure 64. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit ...

Page 41

... PICVCC PICVCC 3 4 GP1 GP1 GP0 5 6 GP0 8 7 MCLR/GP3 MCLR/GP3 9 10 HEADER PROGRAMMING PIC SLOPE GAIN NEGATIVE = SLOPE GAIN POSITIVE PIN MODE 0.018µF 274Ω C420 R416 8 AVDD_5V AVDD_5V 2 1 GAIN LO GAIN HI PIN HILO OPTIONAL AD9287 ...

Page 42

... AD9287 Figure 66. Evaluation Board Schematic, Power Supply Inputs Rev Page Data Sheet 05966-019 GND GND 1 1 GND GND 1 1 ...

Page 43

... Data Sheet Figure 67. Evaluation Board Layout, Primary Side Rev Page AD9287 ...

Page 44

... AD9287 Figure 68. Evaluation Board Layout, Ground Plane Rev Page Data Sheet ...

Page 45

... Data Sheet Figure 69. Evaluation Board Layout, Power Plane Rev Page AD9287 ...

Page 46

... AD9287 Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page Data Sheet ...

Page 47

... SOT- mA, dual Schottky LED 603 Green candela Diode DO-214AB SMC Diode DO-214AA SMC Rev Page AD9287 Manufacturer’s Manufacturer Part Number Murata GRM155R71C104KA88D Murata GRM1555C1H2R2GZ01B Murata GRM219R60J106KE19D Murata GRM188C70J225KE20D Murata GRM155R71H102KA01D AVX ...

Page 48

... AD9287 Item Qty. Reference Designator 17 1 F501 18 1 FER501 19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 20 1 JP301 21 2 J205, J402 22 1 J201 to J204 23 1 J401 24 8 L501, L502, L503, L504, L505, L506, L507, L508 ...

Page 49

... W, 1% tol Switch SMD Light touch, 100GE Transformer CD542 ADT1-1WT, 1:1 impedance ratio transformer IC SOT-223 ADP3339AKC-1.8, 1.5 A, 1.8 V LDO regulator Rev Page AD9287 Manufacturer’s Manufacturer Part Number NIC NRC04F1001TRF Components NIC NRC04J330TRF Components NIC NRC04F4990TRF Components NIC NRC04F1003TRF Components NIC ...

Page 50

... RAM size 64 × MHz speed, PIC12F controller series Rev Page Data Sheet Manufacturer’s Manufacturer Part Number Analog Devices AD8332ACPZ Analog Devices ADP3339AKCZ-5 Analog Devices ADP3339AKCZ-3.3 Analog Devices AD9287BCPZ-100 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ Fairchild NC7WZ07P6X_NL Fairchild NC7WZ16P6X_NL Microchip PIC12F629-I/SN ...

Page 51

... Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel Evaluation Board Rev Page 0.30 0.23 0.18 PIN 1 INDICATOR 5.55 EXPOSED 5.50 SQ PAD 5.45 (BOTTOM VIEW 0.22 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD9287 Package Option CP-48-8 CP-48-8 ...

Page 52

... AD9287 NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05966-0-12/11(E) Rev Page Data Sheet ...

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