AD9289 Analog Devices, AD9289 Datasheet
AD9289
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AD9289 Summary of contents
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... The outputs of each ADC are serialized LVDS with data rates up to 520 Mbps (8 bits × 65 MSPS). 4. The AD9289 operates from a single 3.0 V power supply. 5. The internal clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... AD9289 TABLE OF CONTENTS Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 4 Switching Specifications .............................................................. 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Explanation of Test Levels........................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Equivalent Circuits ........................................................................... 8 REVISION HISTORY 10/04—Initial Version: Revision 0 Typical Performance Characteristics ..............................................9 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 14 Analog Input and Reference Overview ................................... 14 Clock Input and Considerations ...
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... Full VI Full VI Full VI Full V Full V Full V Full IV 2.7 Full IV 2.7 Full VI Full VI Full VI Full VI Full V Rev Page AD9289 Typ Max Unit Bits Guaranteed ±5 ±57 mV ±12 ±68 mV ±0.5 ±2 ±0.2 ±0 ±0.2 LSB ±0.2 ±0.6 LSB ±0.25 LSB ±0.25 ±0.6 LSB ±16 ppm/° ...
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... AD9289 AC SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR) SIGNAL-TO-NOISE RATIO (SINAD) EFFECTIVE NUMBER OF BITS (ENOB) SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST HARMONIC (Second or Third) WORST OTHER (Excluding Second or Third) TWO TONE INTERMOD DISTORTION (IMD) AIN1 and AIN2 = – ...
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... Rev Page Min Typ Max 65 12 6.9 7.7 6.9 7.7 0.5 <1.5 6.9 9.0 11.6 250 250 9.0 9.0 ±100 ±550 ±100 ±500 ±100 ±250 1 4.5 <1 1 STATIC t FRAME STATIC D2 D1 LSB MSB STATIC (N-7) (N-7) (N-6) AD9289 Unit MSPS MSPS ns ns CLK cycles µs ms CLK cycles ns ps rms CLK cycles ...
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... AD9289 ABSOLUTE MAXIMUM RATINGS Table 5. With Respect To Parameter Min ELECTRICAL AVDD AGND –0.3 DRVDD DRGND –0.3 AGND DRGND –0.3 AVDD DRVDD –3.9 Digital Outputs (D1+, DRGND –0.3 D1–, DCO+, DCO–, FCO+, FCO–) LOCK, LVDSBIAS DRGND –0.3 CLK+, CLK– AGND – ...
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... AVDD enable, tie this pin to AVDD. To disable, tie this pin to AGND. 4 DTP has an internal on-chip pull-down resistor. Rev Page AD9289 Description Analog Ground Analog Ground Reference Buffer Decoupling (Positive) Reference Buffer Decoupling (Negative) Voltage Reference Input/Output ...
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... AD9289 EQUIVALENT CIRCUITS AVDD VIN+, VIN– AGND Figure 4. Equivalent Analog Input Circuit AVDD CLK+, CLK– 375Ω AGND Figure 5. Equivalent Clock Input Circuit DRVDD DFS, PDWN, SHARED_REF 375Ω DRGND Figure 6. Equivalent Digital Input Circuit V D1– V Figure 7. Equivalent Digital Output Circuit Figure 8 ...
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... AIN = –0.5dBFS 1V p-p, SFDR (dBc) 2V p-p, SNR (dB) 1V p-p, SNR (dB ENCODE (MSPS) Figure 13. SNR/SFDR vs 10.3 MHz SAMPLE IN 2V p-p, SFDR (dBc) AIN = –0.5dBFS 1V p-p, SFDR (dBc) 2V p-p, SNR (dB) 1V p-p, SNR (dB ENCODE (MSPS) Figure 14. SNR/SFDR vs MHz SAMPLE IN AD9289 ...
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... AD9289 75 60 70dB REFERENCE LINE 50 1V p-p, SFDR (dBc p-p, SNR (dB p-p, SFDR (dBc) 0 –40 –35 –30 –25 –20 ANALOG INPUT LEVEL (dBFS) Figure 15. SNR/SFDR vs. Analog Input Level 2.4 MHz 70dB REFERENCE LINE 50 1V p-p, SFDR (dBc p-p, SNR (dB p-p, SFDR (dBc) 0 – ...
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... MHz Figure 23. Typical DNL 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 Figure 24. Typical INL, f Rev Page AD9289 128 160 192 224 CODE = 2.4 MHz MSPS IN SAMPLE 128 160 192 224 CODE = 2.4 MHz MSPS IN SAMPLE ...
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... AD9289 TERMINOLOGY Analog Bandwidth Analog Bandwidth is the analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced from full scale. Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the 50% point rising edge of the clock input to the time at which the input signal is held for conversion ...
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... The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal levels are lowered dBFS (always related back to converter full scale). Rev Page AD9289 ...
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... This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent on the application. The analog inputs of the AD9289 are not internally dc biased. In ac-coupled applications, the user must provide this bias exter- nally. Setting the device so that V ...
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... Figure 28. Differential Input Configuration Using the AD8351 However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9289. For applications where SNR is a key parameter, differential transfor- mer coupling is the recommended input configuration. An example of this is shown in Figure 29. ...
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... The AD9289 can also support a single-ended CMOS clock. Refer to the evaluation board schematics to enable this feature. Power Dissipation and Standby Mode As shown in Figure 31, the power dissipated by the AD9289 is proportional to its sample rate. The digital power dissipation does not vary because it is determined primarily by the strength of the digital drivers and the load on each output bit ...
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... MSPS = 520 MHz). The lowest typical conversion rate is 12 MSPS. Two output clocks are provided to assist in capturing data from the AD9289. The DCO is used to clock the output data and is equal to four times the sampling clock (CLK) rate. Data is clocked out of the AD9289 and can be captured on the rising and falling edges of the DCO that supports double-data rate operation (DDR) ...
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... VIN–C (–D) REFT_B 0.1µF + 0.1µF 10µF REFB_B SHARED_REF If the internal reference of the AD9289 is used to drive multiple converters to improve gain matching, the loading of the refer- REFT_A ence by the other converters must be considered. Figure 35 0.1µF + depicts how the internal reference voltage is affected by loading. 0.1µF 10µ ...
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... Power and Ground Recommendations V = 1.0V REF When connecting power to the AD9289 recommended that two separate 3.0 V supplies be used. One for analog (AVDD) and one for digital (DRVDD). If only one supply is available then it should be routed to the AVDD first and tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding ...
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... Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 37 shows the typical bench characterization setup used to evaluate the ac performance of the AD9289 critical that ROHDE AND SCHWARZ, SMHU, BAND-PASS ...
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... VIN_A –A VIN F1 VIN_A VIN+A G1 AGND E1 AGND E2 VIN+B VIN_B H2 –B VIN VIN_B H3 AVDD DUT_AVDD F2 AGND G2 Figure 38. Evaluation Board Schematic, DUT, VREF, and Clock Inputs Rev Page AD9289 D1+D CHD B7 –D D1 CHD A7 DNC B8 DNC A8 PDWN E8 CLK+ C8 – CLK D8 DFS C7 VIN_D –D VIN F8 ...
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... AD9289 JP20 JP19 JP18 JP26 JP21 JP24 JP25 Figure 39. Evaluation Board Schematic, DUT Analog Input Rev Page JP29 JP27 JP28 ...
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... AD8351 AD8351 Figure 40. Evaluation Board Schematic, Optional DUT Analog Input Drive Rev Page AD9289 AD8351 AD8351 ...
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... AD9289 JP1 JP4 JP2 Figure 41. Evaluation Board Schematic, Power, and Decoupling Rev Page TP18 TP16 TP15 TP14 ...
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... Figure 42. Evaluation Board Layout, Primary Side Figure 43. Evaluation Board Layout, Primary Side (With Ground Copper Pour) Rev Page AD9289 ...
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... AD9289 Figure 44. Evaluation Board Layout, Ground Plane Figure 45. Evaluation Board Layout, Power Plane Rev Page ...
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... Figure 46. Evaluation Board Layout, Secondary Side Figure 47. Evaluation Board Layout, Secondary Side (With Ground Copper Pour) Rev Page AD9289 ...
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... AD9289 Table 11. Evaluation Board Bill of Materials (BOM) Qnty. per Item Board REFDES 1 1 AD9289 BGA REVA/PCB 2 1 Assembly 3 8 R46, R48, R60, R61, R98, R99, R113, R114 4 8 R5, R7, R8, R9, R10, R17, R33, R39 5 8 R22,R49, R52, R55, R79, R92, R101, R106 ...
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... Rev Page AD9289 Manufacturing Mfg. Part Number Wieland 25.600.5653.0 Amphenol-RF 901-144-8RFX Division Minicircuits ADT1-1WT Molex/Waldom 87267-0850 Electronics Corp Fujitsu FCN-268M012-G/1D Molex/Waldom 87267-0850 Electronics Corp Samtec TSW-120-07-G-S RAF 4040-632-N RAF 3058-N Fairchild 74VHC04MTC Semiconductor Fairchild FIN1017M Semiconductor ADI AD9289BBC-65 ADI ADR510 ADI AD8351ARM ...
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... AD9289 OUTLINE DIMENSIONS 1.70 1.55 1.35 ORDERING GUIDE Model Temperature Range AD9289BBC –40°C to +85°C AD9289-65EB 8.00 BSC BALL A1 INDICATOR 5.60 BSC SQ TOP VIEW 0.80 BSC BOTTOM VIEW DETAIL A DETAIL A 0.34 NOM 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205-BA Figure 48. 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] ...
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... NOTES Rev Page AD9289 ...
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... AD9289 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03682-0-10/04(0) Rev Page ...