AD7451 Analog Devices, AD7451 Datasheet
AD7451
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AD7451 Summary of contents
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... REF PRODUCT HIGHLIGHTS 1. Operation with 2 5.25 V Power Supplies. 2. High Throughput with Low Power Consumption. With supply, the AD7441/AD7451 offer 4 mW maxi- mum power consumption for a 1 MSPS throughput rate. 3. Pseudo Differential Analog Input. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase ...
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... AD7441/AD7451 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 7 Timing Diagrams .......................................................................... 7 Absolute Maximum Ratings ............................................................ 8 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 Circuit Information .................................................................... 13 Converter Operation .................................................................. 13 REVISION HISTORY 3/10— ...
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... SPECIFICATIONS MHz SCLK versions: −40°C to +85°C. Table 1. AD7451 Parameter DYNAMIC PERFORMANCE 1 Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) (SINAD) 1 Total Harmonic Distortion (THD) 1 Peak Harmonic or Spurious Noise Intermodulation Distortion (IMD) 1 Second-Order Terms Third-Order Terms 1 Aperture Delay ...
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... Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result small dc input is applied provide a pseudo ground for V IN– 4 The AD7451 is functional with a reference input in the range of 100 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section. 7 Measured with a full-scale dc input ...
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... Typically 200 μA DD SOURCE 200 μA DD SOURCE I = 200 μA SINK Rev Page AD7441/AD7451 , unless otherwise noted. Temperature range for MAX B Version 61 −72 −73 −72 −74 −80 − 2.5 10 ±0.5 ±0.5 ± ...
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... AD7441/AD7451 Parameter CONVERSION RATE Conversion Time 1 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down 1 See the Terminology section. 2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result. ...
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... V RISE FALL t CONVERT DB11 DB10 Figure 2. AD7451 Serial Interface Timing Diagram t CONVERT DB9 DB8 Figure 3. AD7441 Serial Interface Timing Diagram Rev Page AD7441/AD7451 , unless otherwise noted. ...
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... AD7441/AD7451 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to GND GND IN GND IN– Digital Input Voltage to GND Digital Output Voltage to GND V to GND REF Input Current to any Pin Except Supplies Operating Temperature Range Commercial (A, B Version) ...
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... The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7451 consists of four leading zeros followed by the 12 bits of conversion data that are provided MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of con- version data, followed by two trailing zeros ...
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... SINAD = 71dB 8000 THD = –82dB SFDR = –83dB 7000 6000 5000 4000 3000 2000 1000 400 500 Figure 12. Histogram of 10,000 Conversions Input for the AD7451 = Rev Page 1024 2048 3072 CODE Figure 10. Typical DNL for the AD7451 for ...
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... V 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 Rev Page AD7441/AD7451 8192 POINT FFT f = 1MSPS SAMPLE f = 100kSPS IN SINAD = 61.7dB THD = –81.7dB SFDR = –82dB 100 200 300 400 V (V) REF Figure 16. AD7441 Dynamic Performance 256 512 768 CODE Figure 17 ...
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... The AD7441/AD7451 are tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually dis- ...
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... V ADC TRANSFER FUNCTION The output coding for the AD7441/AD7451 is straight (natural) binary. The designed code transitions occur at successive LSB values (1 LSB, 2 LSB, and so on). The LSB size of the AD7451 is V /4096, and the LSB size of the AD7441 is V REF ideal transfer characteristic of the AD7441/AD7451 is shown in ...
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... V REF 2.5V AD780 0.1µF Figure 22. Typical Connection Diagram ANALOG INPUT The AD7441/AD7451 have a pseudo differential analog input. The V input is coupled to the signal source and must have an IN+ amplitude of V p-p to make use of the full dynamic range of REF the part input is applied to the V IN– ...
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... INPUT FREQUENCY (kHz) Figure 26. THD vs. Analog Input Frequency for Various Supply Voltages DIGITAL INPUTS The digital inputs applied to the AD7441/AD7451 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied, that is, CS and SCLK, can and are not restricted by the V input ...
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... SDATA output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7451 consists of four leading zeros followed by 12 bits of conversion data, provided MSB first. The data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first ...
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... CONVERT 12.5(1/ ) SCLK 1/THROUGHPUT Figure 28. Serial Interface Timing Example Rev Page AD7441/AD7451 = 5 MHz and a throughput rate of 315 kSPS gives a SCLK 1/Throughput = 1/315,000 = 3.174 μ 12.5 (1 3.174 μs 2 SCLK ACQUISITION is 10 ns, then 12.5 (1/5 MHz 3.174 μs ACQUISITION t = 664 ns ...
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... SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. To exit power-down mode and power up the AD7441/AD7451 again, a dummy conversion is performed. On the falling edge the device begins to power up and continues long held low until after the falling edge of the 10th SCLK. The device is fully powered up after 1 μ ...
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... Figure 30. Once supplies are applied to the AD7441/AD7451, the power-up time is the same as that when powering up from power-down mode. It takes approxi- mately 1 μs to power up fully in normal mode not necessary to wait 1 μ ...
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... If the power-up time is one dummy cycle (1 μs) and the remain- ing conversion time is another cycle (1 μs), then the AD7441/ AD7451 can be said to dissipate 9.25 mW for 2 μs during each conversion cycle. (This power consumption figure assumes a very short time to enter power-down mode. This power figure increases as the burst of clocks used to enter power-down mode is increased). The AD7441/AD7451 consume just 5 μ ...
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... Figure 34. Interfacing to the TMS320C5x/C54x AD7441/AD7451 to DSP56xxx The connection diagram in Figure 35 shows how the AD7441/ AD7451 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB) ...
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... PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7441 and the AD7451 evaluation boards, as well as with many other Analog Devices, Inc. evaluation boards ending with the CB designator, to demonstrate and evaluate the ac and dc performance of the AD7441 and the AD7451 ...
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... Figure 36. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters 3.20 3.00 2.80 5. 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 6° 0.40 0.05 0.09 0° 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 37. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev Page AD7441/AD7451 0.60 8° 0.45 0.60 4° 0.30 BSC 0° 0.80 0.55 0.40 ...
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... The evaluation board controller is a complete unit allowing control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, you must order the ADC evaluation board (EVAL-AD7451CB or EVAL-AD7441CB), the EVAL-CONTROL BRD2, and transformer. See the AD7451/AD7441 application note that accompanies the evaluation kit for more information. ...