AD7790 Analog Devices, AD7790 Datasheet
AD7790
Specifications of AD7790
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AD7790 Summary of contents
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... AD7790 GND Figure 1. GENERAL DESCRIPTION The AD7790 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 16-bit ∑-∆ ADC with one differential input that can be buffered or unbuffered along with a digital PGA, which allows gains and 8. ...
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... AD7790 TABLE OF CONTENTS AD7790—Specifications.................................................................. 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 On-Chip Registers .......................................................................... 10 Communications Register (RS1, RS0 = 0, 0) ......................................................................... 10 Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x88)............................... 11 Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 11 Filter Register (RS1, RS0 = 1, 0 ...
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... Input current varies with input voltage typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 typ, 50 ± 1 Hz, FS[2:0] = 101 typ, 60 ± 1 Hz, FS[2:0] = 011 Input Range = ±REFIN, AIN = 100 dB typ (FS[2:0] = 100 ) 4 50 ± (FS[2:0] = 101 ), 60 ± (FS[2:0] = 011 REFIN = REFIN(+) – REFIN(– V). DD AD7790 ...
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... I Current DD I (Power-Down Mode Digital inputs equal GND The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15). 1 AD7790B Unit 65 dB min 80 dB min 80 dB min 100 dB typ 110 dB typ 0.8 V max ...
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... SCLK Inactive Edge to DOUT/RDY High CS Falling Edge to SCLK Active Edge Setup Time Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time CS Rising Edge to SCLK Edge Hold Time = (10 and timed from a voltage level of 1 limits AD7790 4 4 ...
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... AD7790 DOUT/RDY (O) I (1.6mA WITH V SINK 100µA WITH V TO OUTPUT 1.6V PIN 50pF I (200µA WITH V SOURCE 100µA WITH V Figure 2. Load Circuit for Timing Characterization CS ( MSB SCLK ( INPUT OUTPUT Figure 3. Read Cycle Timing Diagram ...
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... Exposure to absolute –0 0.3 V maximum rating conditions for extended periods may affect DD –0 0.3 V device reliability. DD –40°C to +105°C –65°C to +150°C 150°C 206°C/W 44°C/W 300°C 220°C Rev Page AD7790 ...
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... AD7790 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK AD7790 AIN(+) 3 TOP VIEW 8 (Not to Scale) AIN(– REF(+) 5 6 03538-0-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications ...
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... FREQUENCY (Hz) Figure 6. Frequency Response for a 16.6 Hz Update Rate 3.0 2.5 2.0 1.5 1.0 0.5 0 120 140 160 03538-0-007 Rev Page UPDATE RATE = 16.6Hz T = 25° 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V (V) REF Figure 7. RMS Noise vs. Reference Voltage AD7790 4.5 5.0 03538-0-013 ...
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... AD7790 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com- munications register ...
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... SR3 1 This bit is automatically set. SR2 0 This bit is automatically cleared if the device is an AD7790. It can be used to distinguish between the AD7790 and AD7791, in which the bit is set. SR1–SR0 CH1–CH0 These bits indicate which channel is being converted by the ADC. MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02) The mode register is an 8-bit register from which data can be read or to which data can be written ...
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... Bit Name Description FR7–FR6 0 These bits must be programmed with a Logic 0 for correct operation. FR5–FR4 CLKDIV1– These bits are used to operate the AD7790 in the lower power modes. The clock is internally divided and CDIV0 the power is reduced FR3 0 This bit must be programmed with a Logic 0 for correct operation ...
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... When the internal clock is reduced, the update rate will also be reduced. For example, if the filter bits are set to give an update rate of 16.6 Hz when the AD7790 is operated in full clock mode, the update rate will equal 8 divide by 2 mode. In these low power modes, there may be some degradation in the ADC performance. Typ Current, Unbuffered (µ ...
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... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7790 line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in 3-wire systems, the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system ...
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... Single Conversion Mode In single conversion mode, the AD7790 is placed in shutdown mode between conversions. When a single conversion is initi- ated by setting MD1 to 1 and MD0 the mode register, the AD7790 powers up, performs a single conversion, and then returns to shutdown mode. A conversion will require a time period of 2 × ...
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... If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7790 to read the word, the serial output register is reset when the next conver- sion is complete and the new conversion is placed in the output serial register ...
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... V, ±625 mV, or ±312.5 mV. These are the ranges that should appear at the input to the on-chip PGA. BIPOLAR CONFIGURATION The analog input to the AD7790 accepts a bipolar input voltage range. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system GND. Bipolar signals on the AIN(+) input are referenced to the voltage on the AIN(– ...
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... A minimum etch technique is generally best for ground planes because it gives the best shielding recommended that the AD7790’s GND pin be tied to the AGND plane of the system. In any layout important that the user keep in mind the flow of currents in the system, ensur- ing that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations ...
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... COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA Figure 11. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Package Description 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) Rev Page 0.80 8° 0.60 0° 0.40 Package Option RM-10 RM-10 AD7790 Branding COS COS ...
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... AD7790 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective companies. C03538-0-8/03(0) Rev Page ...