AD9878 Analog Devices, AD9878 Datasheet
AD9878
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AD9878 Summary of contents
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... The AD9878 includes a programmable ∑-∆ DAC, which can be used to control an external component such as a variable gain amplifier (VGA voltage controlled tuner. The AD9878 also integrates a CA port that enables a host processor to interface with the AD832x family of programmable gain amplifier (PGA) cable drivers or industry equivalent via the MxFE serial port (SPORT) ...
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... AD9878 TABLE OF CONTENTS Electrical Characteristics ................................................................. 4 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 Thermal Characteristics .............................................................. 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 13 Register Bit Definitions.................................................................. 14 Register 0x00—Initialization .................................................... 15 Register 0x01—Clock Configuration....................................... 15 Register 0x02—Power-Down.................................................... 15 Register 0x03—Flag Control..................................................... 15 Register 0x04— ...
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... Changes to Electrical Characteristics ........................................................4 Changes to Pin Configuration and Function Descriptions....................8 Changes to ∑-∆ Output Signals (Figure 32)............................................27 Change to ∑-∆ RC Filter (Figure 33) .......................................................27 Changes to Evaluation PCB Schematic (Figure 38 and Figure 39)......31 Updated Outline Dimensions...................................................................36 Changes to Ordering Guide......................................................................36 5/03—Revision 0: Initial Version Rev Page AD9878 ...
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... AD9878 ELECTRICAL CHARACTERISTICS V = 3.3 V ± 5 3.3 V ± 10 OSCIN R = 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load. SET Table 1. PARAMETER OSCIN and XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Impedance MCLK Cycle-to-Cycle Jitter (f derived from PLL) MCLK Tx DAC CHARACTERISTICS ...
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... Full II 46.7 53 Full II 54.3 63.2 Full II −50.2 Full II 45.9 50 25°C III >60 25°C III >80 25°C III >85 25°C III >85 Rev Page AD9878 Max Unit dB Bits −56 Bits MHz ADC cycles V PPD kΩ|| rms MHz µV +100 mV dB Bits dB −61 Bits dB −61.8 ...
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... AD9878 PARAMETER TIMING CHARACTERISTICS (10 pF Load) Wake-Up Time Minimum RESET Pulse Width Low Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency, f MCLK TxSYNC/TxIQ Setup Time TxSYNC/TxIQ Hold Time MCLK Rising Edge to RxSYNC Valid Delay, t REFCLK Rising or Falling Edge to RxSYNC Valid Delay, t ...
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... II. Parameter is guaranteed by design and/or characterization testing. III. Parameter is a typical value only. N/A. Test level definition is not applicable. THERMAL CHARACTERISTICS Thermal resistance of 100-lead LQFP: θ Rev Page AD9878 = 40.5°C/W JA ...
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... RESET 41 SCLK SDIO AD9878 TOP VIEW (Not to Scale Figure 2. Pin Configuration Descriptions Pin Driver Digital Ground Pin Driver Digital 3.3 V Supply 12-Bit ADC Digital Ouput 12-Bit ADC Digital Ouput ...
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... ADC Analog Ground Differential Input to 10-bit ADC 12-Bit ADC Analog 3.3 V Supply ADC12B Reference Decoupling Node ADC12B Reference Decoupling Node Differential Input to ADC12B ADC12A Reference Decoupling Node ADC12A Reference Decoupling Node Differential Input to ADC12A Video Clamp Input Rev Page AD9878 ...
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... AD9878 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (MHz) Figure 3. Dual-Sideband Spectral Plot kΩ mA), RBW = 1 kHz SET OUT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 ...
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... MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 100 120 –2.5 –2.0 Figure 14. Single Sideband @ 65 MHz MHz, R Rev Page AD9878 100 FREQUENCY (MHz MHz kΩ mA), RBW = 2 kHz SET OUT –1.5 –1.0 –0.5 0 0.5 1 ...
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... AD9878 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –50 –40 –30 –20 – FREQUENCY (MHz) Figure 15. Single Sideband @ 65 MHz MHz kΩ mA), RBW = 50 Hz SET OUT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 – ...
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... In an ideal multichannel system, the signal in one channel does not influence the signal level of another channel. The channel- to-channel isolation specification is a measure of the change that occurs in a grounded channel as a full-scale signal is applied to another channel. Rev Page AD9878 . 6 02 ...
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... AD9878 REGISTER BIT DEFINITIONS Table 4. Register Map Address (Hex) Bit 7 Bit 6 Bit 5 0x00 SDIO LSB Reset bidirectional first 0x01 PLL lock detect 0x02 Power down Power Power PLL down down DAC digital Tx Tx 0x03 Video input into ADC12B 0x04 MSB/Flag 0 0x05 ...
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... Bit 7: Flag 0 (∑-∆ Control Word MSB) When the Flag 0 enable bit (Register 0x03, Bit 0) is set, the logic level of this bit appears on the output of the SIGDELT pin. Rev Page AD9878 ...
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... Active high configures the AD9878 to bypass the sin(x)/x com- pensation filter. Default value is 0x00 (inverse sinc filter enabled). Bit 3: CA Interface Mode Select This bit changes the format of the AD9878 3-wire CA interface to a format in which the AD9878 digitally interfaces to external variable gain amplifiers. This is accomplished by changing the interpretation of the bits in Register 0x13, Register 0x17, Register 0x1B, and Register 0x1F ...
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... DAC Fine Gain (dB) 0.0 (default) 0.5 1.0 1.5 … 7.0 7 − V fine 2 coarse 8327 9878 − V fine 2 coarse 8322 9878 0 is the level at AD9878 output in dBmV for fine = 0. AD9878 ...
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... AD9878 and to run the serial port state machine. The maximum SCLK frequency is 15 MHz. Input data to the AD9878 is sampled up on the rising edge of SCLK. Output data changes upon the falling edge of SCLK. CS —Chip Select. Active low input starts and gates a commu- nication cycle ...
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... SDO Figure 22. Serial Register Interface Timing, LSB-First Mode NOTES ON SERIAL PORT OPERATION The AD9878 serial port configuration bits reside in Bit 6 and Bit 7 of Register Address 0x00. Note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register might occur during a communication cycle ...
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... The 12-bit and 10-bit IF ADCs can convert direct IF inputs MHz and run at sample rates MSPS. A video input with an adjustable signal clamping level, along with the 10-bit ADC, allow the AD9878 to process an NTSC and a QAM channel simultaneously. The programmable ∑-∆ DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage- controlled tuners ...
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... SNR when reduced output levels are required. DATA ASSEMBLER The AD9878 data path operates on two 12-bit words, the I and Q components, that form a complex symbol. The data assembler builds the 24-bit complex symbol from four consecutive 6-bit words read over the TxIQ [5:0] bus ...
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... AD9878 been pulse shaped, there is an additional concern. Typically, pulse shaping is applied to the baseband data via a filter with a raised cosine response. In such cases, an α value is used to modify the bandwidth of the data, where the value of α is such that < α < value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwidth. Thus, with 2× ...
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... SYSCLK like a 25 Ω load to the AD9878. The output compliance voltage of the AD9878 is −0 +1.5 V. Any signal developed at the cycles) to MCLK DAC output should not exceed 1.5 V; otherwise, signal distortion results. Furthermore, the signal can extend below ground as much as 0 ...
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... Upon a software reset, the AD9878 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. The AD9878 writes all 0s out of the 3-wire cable amplifier control interface if the gain is previously on a different setting (different from 0). ...
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... AD9878 TOP VIEW (Not to Scale C13 0.1µF Figure 29. Basic Connection Diagram Rev Page AD9878 CP1 10µ 0.1µF 0.1µF 0.1µ REFT10 75 REFB10 74 AGND10 73 AVDD10 72 DRVDD 71 DRGND 70 REFCLK 69 SIGDELT ...
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... Upon initial power-up, the RESET pin should be held low until the power supply is stable (see Figure 30). Once RESET is deasserted, the AD9878 can be programmed over the serial port. The on- chip PLL requires a maximum after the rising edge of RESET or a change of the multiplier factor (M) to completely settle ...
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... Figure 34. ∑-∆ Active Filter with Gain and Offset RECEIVE PATH (Rx) The AD9878 includes three high speed, high performance ADCs. The 10-bit and dual 12-bit direct-IF ADCs deliver excellent under- sampling performance with input frequencies as high as 70 MHz. The sampling rate can be as high as 29 MSPS. The ADC sampling frequency can be derived directly from the OSCIN signal, or from the on-chip OSCIN multiplier ...
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... Figure 35. Simple ADC Drive Configuration Receive Timing The AD9878 sends multiplexed data to the IF10 and IF12 outputs upon every rising edge of MCLK. RxSYNC frames the start of each IF10 data symbol. The 10-bit and 12-bit ADCs are read completely upon every second MCLK cycle. RxSYNC is high for every second 10-bit ADC data if the 10-bit ADC is not in power-down mode ...
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... ADC VOLTAGE REFERENCES The AD9878 has three independent internal references for its 10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are designed for 2 V p-p input voltages and have their own internal reference. Figure 29 shows the proper connections of the REFT and REFB reference pins. External references might be necessary ...
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... AD9878, an AVDD section that is used to supply the analog supply pins of the AD9878, and a VANLG section that supplies the higher voltage analog components on the board. The 3-V section typically has the highest frequency currents on the power plane and should be kept the furthest from the MxFE and analog sections of the board ...
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... CC0603 RCOM 1 CC0603 XTAL OSCIN CC0603 BCASE CC0603 CC0603 CC0805 CC0805 Figure 38. Evaluation PCB Schematic Rev Page AD9878 03277-038 RC07CUP CC0603 CC0603 BCASE BCASE CC0603 CC0603 CC0603 CC0603 CC0805 RC0805 CC0805 CC1206 CC1206 RC0805 CC0805 CC0805 BCASE ...
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... AD9878 PORT PARALLEL PC GND3 TSSOP24 17 74LVXC3245 VCCB 24 DVDD CA_SLEEP GND3 DEL_CLK DEL_CLK B5 JP6 TSSOP24 CLK INVERT B3 JP5 18 74LVXC3245 ...
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... Figure 40. Evaluation PCB—Top Assembly Figure 41. Evaluation PCB—Bottom Assembly Rev Page AD9878 ...
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... AD9878 Figure 42. Evaluation PCB Layout—Top Layer Figure 43. Evaluation PCB Layout—Bottom Layer Rev Page ...
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... Figure 44. Evaluation PCB—Power Plane Figure 45. Evaluation PCB—Ground Plane Rev Page AD9878 ...
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... ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9878BST −40°C to +85°C 1 AD9878BSTZ −40°C to +85°C AD9878- Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 1.60 MAX 0.75 100 1 ...