AD7476A Analog Devices, AD7476A Datasheet
AD7476A
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AD7476A Summary of contents
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... Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit high speed, low power, successive-approximation analog-to- digital converters (ADCs), respectively. The parts operate from a single 2. 5.25 V power supply and feature throughput rates MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz ...
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... Power-Up Time .......................................................................... 18 Power vs. Throughput Rate ........................................................... 20 Serial Interface ................................................................................ 21 AD7478A SCLK Cycle Serial Interface ....................... 22 Microprocessor Interfacing ........................................................... 23 AD7476A/AD7477A/AD7478A to TMS320C541 Interface 23 AD7476A/AD7477A/AD7478A to ADSP-218x Interface .... 23 AD7476A/AD7477A/AD7478A to DSP563xx Interface ...... 24 Application Hints ........................................................................... 25 Grounding and Layout .............................................................. 25 Evaluating the AD7476A/AD7477A Performance ............... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26 Automotive Products ................................................................. 27 Rev Page ...
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... SPECIFICATIONS AD7476A SPECIFICATIONS MHz SCLK Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Signal-to-Noise Ratio (SNR) 3 Total Harmonic Distortion (THD) 3 Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) 3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter ...
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... AD7476A/AD7477A/AD7478A Parameter LOGIC OUTPUTS Output High Voltage Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance 6 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time 3 Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) ...
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... Straight (Natural) Binary 700 ns max 250 ns max 1 MSPS max Rev Page AD7476A/AD7477A/AD7478A 1 Test Conditions/Comments f = 100 kHz sine wave 100.73 kHz 90.7 kHz fa = 100.73 kHz 90.7 kHz @ 0.1 dB Guaranteed no missed codes to 10 bits Track-and-hold in track typ when in hold ...
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... AD7476A/AD7477A/AD7478A Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation 6 Normal Mode (Operational) Full Power-Down Mode Temperature range is from –40°C to +85° Operational from V = 2.0 V, with input high voltage (V ...
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... V minimum. INH Rev Page AD7476A/AD7477A/AD7478A Test Conditions/Comments Typically 10 nA 200 μ 2. 5.25 V SOURCE 200 μA SINK 12 SCLK cycles with SCLK at 20 MHz ...
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... Unit Description kHz min A, B grades 3 kHz min 3 Y grade MHz max AD7476A AD7477A AD7478A ns min Minimum quiet time required between bus relinquish and start of next conversion ns min Minimum CS pulse width ns min CS to SCLK setup time ns max Delay from CS until SDATA three-state disabled ...
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... Point C in Figure 4. , QUIET t CONVERT ZERO DB11 DB10 DB2 Figure 3. AD7476A Serial Interface Timing Diagram t CONVERT 12.5(1/f ) SCLK 1/THROUGHPUT Figure 4. Serial Interface Timing Example Rev Page AD7476A/AD7477A/AD7478A = 5 MHz and a throughput is 315 kSPS yields a SCLK + 12.5 (1 3.174 µ ...
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... AD7476A/AD7477A/AD7478A ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted Table 5. Parameter V to GND DD Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies Operating Temperature Range Commercial (A and B Grades) Industrial (Y Grade) Storage Temperature Range ...
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... Data Out. Logic output. The conversion result from AD7476A/AD7477A/AD7478A is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four leading zeros followed by 12 bits of conversion data that are provided MSB first. The data stream from the AD7477A consists of four leading zeros followed by 10 bits of conversion data followed by two trailing zeros, provided MSB first ...
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... FREQUENCY (kHz) Figure 8. AD7477A Dynamic Performance at 1 MSPS Figure 11 and Figure 12 show INL and DNL performance for the AD7476A. Figure 13 shows a graph of the total harmonic distortion vs. the analog input frequency for different source impedances when using a supply voltage of 3.6 V and sampling at a rate of 1 MSPS (see the Analog Input section) ...
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... V = 2.35V 0.8 DD TEMP = 25°C f 0.6 SAMPLE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 3072 CODE Figure 11. AD7476A INL Performance 1 0.8 TEMP = 25°C f SAMPLE 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 3072 CODE Figure 12. AD7476A DNL Performance 0 –10 = 1MSPS – ...
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... The AD7476A/AD7477A/AD7478A are tested using the CCIF standard where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms ...
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... V IN SW1 B AGND ADC TRANSFER FUNCTION The output coding of the AD7476A/AD7477A/AD7478A is straight binary. The designed code transitions occur at the successive integer LSB values, that is, 1 LSB, 2 LSB, and so on. The LSB size is V AD7477A, and V characteristic for the AD7476A/AD7477A/AD7478A is shown in Figure 17. ...
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... V), resulting in an error ppm (51 µV) for the 1.7 mA drawn from it. This corresponds to a 0.069 LSB error for the AD7476A with V REF193, a 0.017 LSB error for the AD7477A, and a 0.0043 LSB error for the AD7478A. For applications where power consumption is a concern, use the power-down mode of the ADC and the sleep mode of the REF19x reference to improve power performance ...
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... Table 8 provides typical performance data with various op amps used as the input buffer for a 100 kHz input tone at room temperature under the same setup conditions. Table 8. AD7476A Typical Performance with Various Input Buffers Amp in the Input Buffer AD7476A SNR Performance (dB) AD711 72 ...
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... SCLK falling edge but before the end of the t remains powered up, but the conversion is terminated and SDATA goes back into three-state. For the AD7476A, 16 serial clock cycles are required to complete the conversion and access the complete conversion results. For the AD7477A and AD7478A, ...
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... A 1 SCLK SDATA When power supplies are first applied to the AD7476A/AD7477A/ AD7478A, the ADC can power up in either the power-down or normal modes. Because of this best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise intended to keep ...
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... V). If the power-up time is one dummy cycle, that is μs, and the remaining conversion time is another cycle, that is, 1 μs, then the AD7476A/AD7477A/AD7478A dissipate 17.5 mW for 2 μs during each conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs, then the average power dissipated during each cycle is (2/10) × ...
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... Also, the conversion is initiated at this point. For the AD7476A, the conversion requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track- and-hold goes back into track on the next SCLK rising edge, as shown in Figure 24 at Point B ...
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... Thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. For the AD7476A, the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge ...
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... Serial Clock CLKX (MCM = 1 in the SPC register) and internal frame signal (TXM = 1 in the SPC register), so both pins are configured as outputs. For the AD7476A, set the word length to 16 bits ( the SPC register). This DSP only allows frames with a word length of 16 bits or 8 bits. Therefore, in the case of the AD7477A and AD7478A where 14 bits and 12 bits are required, the FO bit is set bits ...
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... FSL1 = 0 and Bit FSL0 = 0 in CRB). Set the word length in Control Register A (CRA setting Bit WL2 = 0, Bit WL1 = 1, and Bit WL0 = 0 for the AD7476A. The word length for the AD7478A can be set to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This DSP does not offer the option for a 14-bit word ...
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... APPLICATION HINTS GROUNDING AND LAYOUT Design the printed circuit board that houses the AD7476A/ AD7477A/AD7478A such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding ...
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... AD7476ABRM-REEL7 –40°C to +85°C AD7476ABRMZ –40°C to +85°C AD7476ABRMZ-REEL –40°C to +85°C AD7476ABRMZ-REEL7 –40°C to +85°C AD7476AWYRMZ –40°C to +125°C AD7476AWYRMZ-RL7 –40°C to +125°C AD7476AYKSZ-500RL7 –40°C to +125°C AD7476AYKSZ-REEL7 –40°C to +125°C AD7476AYRMZ – ...
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... EVAL-CONTROL BRD2 is a complete unit, allowing control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a 4 complete evaluation kit, you will need to order the particular ADC evaluation board, for example, EVAL-AD7476ACB, the EVAL-CONTROLBRD2, and transformer. See relevant evaluation board application note for more information. ...
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... AD7476A/AD7477A/AD7478A NOTES ©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02930-0-1/11(F) Rev Page ...