AD7782 Analog Devices, AD7782 Datasheet

no-image

AD7782

Manufacturer Part Number
AD7782
Description
2-Channel, Read-Only, Pin-Configured, 24-bit Sigma-Delta ADC
Manufacturer
Analog Devices
Datasheet

Specifications of AD7782

Resolution (bits)
24bit
# Chan
2
Sample Rate
4.2MSPS
Interface
Ser,SPI
Analog Input Type
Diff-Bip
Ain Range
0.32 V p-p,5.12 V p-p
Adc Architecture
Sigma-Delta
Pkg Type
SOP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7782BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
a
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
GENERAL DESCRIPTION
The AD7782 is a complete analog front end for low-frequency
measurement applications. The 24-bit sigma-delta ADC contains
two fully differential analog input channels that can be config-
ured with a gain of 1 or 16 allowing full-scale input signal ranges
of ± 2.56 V or ± 160 mV from a +2.5 V differential reference
input.
The AD7782 has an extremely simple, read-only digital interface
which can be operated in master mode or slave mode. There are
no on-chip registers to be programmed. The input signal range
and input channel selection are configured using two external pins.
The device operates from a 32.768 kHz crystal with an on-chip PLL
generating the required internal operating frequency. The output
data rate from the part is fixed via the master clock at 19.79 Hz and
provides simultaneous 50 Hz and 60 Hz rejection at this update
rate. Eighteen-bit p-p resolution can be obtained at this update rate.
The part operates from a single 3 V or 5 V supply. When operating
from 3 V supplies, the power dissipation for the part is 3.9 mW.
The AD7782 is available in a 16-lead TSSOP package.
Another part in the AD778x family is the AD7783. It is similar
to the AD7782 except it has two integrated current sources and
only one differential input channel.
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
CH1/CH2
REFERENCE
MUX
V
Read Only, Pin Configured
DD
ANALOG
ANALOG
FUNCTIONAL BLOCK DIAGRAM
BASIC CONNECTION DIAGRAM
INPUT
INPUT
INPUT
AD7782
BUF
GND
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
REFIN(+)
REFIN(–)
RANGE
PGA
POWER SUPPLY
AD7782
REFIN(+)
GND
V
DD
24-Bit - ADC
24-BIT -
DOUT/RDY
ADC
XTAL1
XTAL2
SCLK
REFIN(–)
CS
XTAL1 XTAL2
OSCILLATOR
INTERFACE
AD7782
CONTROL
32.768kHz
CRYSTAL
SERIAL
LOGIC
DIGITAL
INTERFACE
AND
AND
PLL
DOUT/RDY
SCLK
MODE
CS

Related parts for AD7782

AD7782 Summary of contents

Page 1

... V supplies, the power dissipation for the part is 3.9 mW. The AD7782 is available in a 16-lead TSSOP package. Another part in the AD778x family is the AD7783 similar to the AD7782 except it has two integrated current sources and only one differential input channel. AD7782 ...

Page 2

... V T(+) T(–) V T(+) V T(–) V – V T(+) T(– 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T AD7782B Unit 19.79 Hz nom 24 Bits min 16 Bits p-p 18 Bits p-p See Table I ± 10 ppm of FSR max ± 3 µV typ ± ...

Page 3

... V max ± 10 µA max ± typ Offset Binary 300 ms typ 2.7/3.6 V min/max 4.75/5.25 V min/max 1.5 mA max 1.7 mA max µA max 9 µA max 24 AD7782 Test Conditions GND, Typically –40 µ and –20 µ ...

Page 4

... AD7782 TIMING CHARACTERISTICS Limit at T Parameter (B Version) t 30.5176 1 t 50.54 ADC × ADC Slave Mode Timing t 100 6 t 100 7 Master Mode Timing ...

Page 5

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7782 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 6

... SCLK is Schmitt triggered (slave mode) making the interface suitable for opto- isolated applications. CS Chip Select Input active low logic input used to select the AD7782. When CS is low, the PLL 11 establishes lock and allows the AD7782 to initiate a conversion on the selected channel. When CS is high, the conversion is aborted, DOUT and SCLK are three-stated, the AD7782 enters standby mode and any conversion result in the output shift register is lost ...

Page 7

... The output rate of the AD7782 (f while the settling time equals: Normal-mode rejection is the major function of the digital filter on the AD7782. Simultaneous 50 Hz and 60 Hz rejection of better than achieved as notches are placed at both 50 Hz and 60 Hz. Figure 4 shows the filter rejection. ...

Page 8

... Figure 2 shows the timing diagram for interfacing to the AD7782 with CS used to decode the part. MASTER MODE (MODE = 0) In this mode, SCLK is provided by the AD7782. With CS low, SCLK becomes active when a conversion is complete and generates twenty four falling and rising edges. The DOUT/RDY pin, which is normally high, goes low to indicate that a conversion is complete ...

Page 9

... As a result, the AD7782 is more immune to noise inter- ference than a conventional high-resolution converter. However, because the resolution of the AD7782 is so high, and the noise levels from the AD7782 so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7782 should be designed such that the analog and digital sections are separated and confined to certain areas of the board ...

Page 10

... AD7782 SEATING OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Thin Shrink SO Plastic (TSSOP) (RU-16) 0.201 (5.10) 0.193 (4.90 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) ...

Page 11

...

Page 12

...

Related keywords