AD9433 Analog Devices, AD9433 Datasheet
AD9433
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AD9433 Summary of contents
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... The AD9433 maintains outstanding ac performance up to input frequencies of 350 MHz. Suitable for 3G wideband cellular IF sampling receivers. 2. Pin-Compatibility with the AD9432. The AD9433 has the same footprint and pin layout as the AD9432 12-bit 80 MSPS/105 MSPS ADC. 3. SFDR Performance. A user-selectable, on-chip circuit optimizes SFDR performance as much as 83 dBc from MHz ...
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... SFDR Optimization.................................................................... 18 Digital Outputs ........................................................................... 18 Voltage Reference ....................................................................... 18 Timing ......................................................................................... 18 Applications Information .............................................................. 19 Layout Information .................................................................... 19 Replacing the AD9432 with the AD9433 ................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20 Rev Page ...
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... VI 12 ±3 V 3.75 V 500 IV −0 0. 2.0 4. 2 Rev Page AD9433 125 MSPS Min Typ Max Unit 12 Bits Guaranteed − −7 ± −0.75 ±0.3 +0.75 LSB −1 +1 LSB −1.0 ±0.5 +1.0 LSB −1.3 +1.3 LSB −50 ppm/° ...
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... AD9433 Parameter Temp DIGITAL OUTPUTS Logic 1 Voltage Full Logic 0 Voltage Full Output Coding 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and p-p differential analog input). 2 SFDR mode disabled (SFDR MODE = GND) for DNL and INL specifications. ...
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... Out-of-Range Recovery Time Transient Response Time Latency 1 Aperture uncertainty includes contribution of the AD9433, crystal clock reference, and encode drive circuit and t are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is not ...
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... Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range. THERMAL CHARACTERISTICS Table 5 lists AD9433 thermal characteristics for simulated typical Rating performance in a 4-layer JEDEC board, horizontal orientation. −0 +6.0 V −0 +6.0 V Table 5. Thermal Resistance − ...
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... Data Format Select. Logic low = twos complement, logic high = offset binary; floats low. CMOS Control Pin. This pin enables SFDR mode, a proprietary circuit that can improve the SFDR performance of the AD9433. SFDR mode is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by nonlinearities in the ADC transfer function. Set this pin to 0 for normal operation ...
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... AD9433 TYPICAL PERFORMANCE CHARACTERISTICS 0 SNR = 67.5dB –10 SFDR = 85dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 13.1 26.3 FREQUENCY (MHz) Figure 4. FFT 105 MSPS 49.3 MHz, Differential AIN @ −0.5 dBFS SFDR Mode Enabled 0 SNR = 68dB –10 SFDR = 80dBFS –20 – ...
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... AIN (MHz 125 MSPS, SFDR Mode Enabled S THIRD HARMONIC SECOND HARMONIC SNR 0 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 AIN COMMON-MODE VOLTAGE (V) Differential AIN @ −0.5 dBFS 49.3 MHz 105 MSPS IN S +25°C +85°C 10.3 49.3 80.3 170.3 AIN (MHz) Differential AIN, SFDR Mode Disabled AD9433 11.3 10.9 10.6 10.3 9.9 9.6 9.3 8.9 250.3 4.4 4.5 –40°C 250.3 = 105 MSPS, S ...
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... AD9433 –95 WORST OTHER (dBc) –90 THIRD HARMONIC (dBc) –85 –80 SECOND HARMONIC (dBc) –75 SNR (dB) –70 – DUTY CYCLE HIGH (%) Figure 16. Dynamic Performance vs. Encode Duty Cycle 49.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled IN 0.75 0.50 0.25 0 –0.25 – ...
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... AIN LEVEL (dBFS) = 105 MSPS Differential AIN, SFDR Mode Enabled –90 –80 –70 –60 –50 –40 –30 –20 AIN LEVEL (dBFS) = 105 MSPS and 69.3 MHz, Differential AIN, SFDR Mode Enabled AD9433 45.0 52.5 – 70.3 MHz, IN – 70.3 MHz IN ...
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... AD9433 0 SNR = 64dB –10 SFDR = 78dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 7.5 15.0 22.5 30.0 FREQUENCY (MHz) Figure 28. FFT 105 MSPS 150.3 MHz, Differential AIN @ −0.5 dBFS SFDR Mode Enabled 0 SNR = 61.2dB –10 SFDR = 67dBFS –20 –30 –40 – ...
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... Figure 34. FFT 76.8 MSPS 59.6 MHz, Two WCDMA Carriers Differential AIN, SFDR Mode Enabled 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 28.8 38.4 Figure 35. FFT: f Rev Page AD9433 11.52 23.04 34.56 46.08 FREQUENCY (MHz) = 92.16 MSPS 70.3 MHz, WCDMA @ 70.0 MHz SFDR Mode Enabled ...
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... AD9433 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled ...
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... Worst Other Spur , the rms The ratio of the rms signal amplitude to the rms value of the 1 2 worst spurious component (excluding the second-order and − f and 2f − third-order harmonic); reported in dBc Rev Page AD9433 , the rms 1 2 ...
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... AD9433 EQUIVALENT CIRCUITS V CC VREFIN Figure 36. Voltage Reference Input Circuit V CC 3.75kΩ 3.75kΩ AIN AIN 15kΩ 15kΩ Figure 37. Analog Input Circuit Figure 38. Digital Output Circuit V Figure 39. Voltage Reference Output Circuit 8kΩ ENCODE 24kΩ Figure 40. Encode Input Circuit Rev ...
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... ADC output. For this reason, considerable care has been taken in the design of the encode input of the AD9433, and the user is advised to give commensurate thought to the clock source. The AD9433 has an internal clock duty cycle stabilization ...
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... Driving the ADC single-ended degrades performance, partic- ularly even-order harmonics. For best dynamic performance, impedances at AIN and AIN should match. Special care was taken in the design of the analog input section of the AD9433 to prevent damage and corruption of data when the input is overdriven. ...
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... The encode clock must be isolated from the digital outputs and the analog inputs. REPLACING THE AD9432 WITH THE AD9433 The AD9433 is pin-compatible with the AD9432, although there are two control pins on the AD9433 that are do not connect (DNC) and supply (V ) connections on the AD9432 (see Table 10). CC Table 10 ...
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... ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range 1 AD9433BSVZ-105 −40°C to +85°C 1 AD9433BSVZ-125 −40°C to +85° RoHS Compliant Part. ©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 12.00 BSC SQ ...