AD7665 Analog Devices, AD7665 Datasheet
AD7665
Specifications of AD7665
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AD7665 Summary of contents
Page 1
... CMOS process and is available in a 48-lead LQFP and a tiny 48-lead LFCSP with operation specified from –40°C to +85°C. PRODUCT HIGHLIGHTS 1. Fast Throughput The AD7665 is a very high speed (570 kSPS in Warp Mode and 500 kSPS in Normal Mode), charge redistribution, 16-bit SAR ADC. 2. Single-Supply Operation ...
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... AD7665–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise ...
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... Symbol –3– AD7665 Typ Max 107 7 +85 Input INA(R) Impedance REF 5.85 kW REF 3.41 kW REF 2.56 kW INGND 3.41 kW INGND 2. Note 3 IN Min Typ Max 5 1.75/2/2.25 Note 1 30 ...
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... AD7665 TIMING SPECIFICATIONS (continued) Parameter Refer to Figures 17 and 18 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Read during Convert) (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7665 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD7665 Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 44– Connect. 4 BYTESWAP Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. ...
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... DI enabled also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7665. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed ...
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... Aperture Delay A measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7665 to achieve its rated accuracy after a full-scale step function is applied to its input. –8– ...
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... POSITIVE INL – LSB TPC 3. Typical Positive INL Distribution (446 Units) C REV. Typical Performance Characteristics–AD7665 TPC 4. Typical Negative INL Distribution (446 Units) 8000 7000 6000 5000 4000 3000 2000 1000 TPC 5. Histogram of 16,384 Conversions Input at the Code Transition ...
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... AD7665 –0 –20 –40 –60 –80 –100 –120 –140 –160 –180 0 57 114 171 FREQUENCY – kHz TPC 7. FFT Plot 100 95 SNR 90 SINAD FREQUENCY – kHz TPC 8. SNR, S/(N+D), and ENOB vs. Frequency –80 –70 –60 –50 –40 – ...
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... TPC 15. Power-Down Operating Currents vs. Temperature L 10 –2 –4 OVDD, ALL MODES –6 –8 –10 10000 100000 1000000 TPC 16. +FS, Offset, and –FS vs. Temperature –11– AD7665 OVDD 0 –55 –35 – TEMPERATURE – –FS OFFSET 2 ...
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... It is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. The AD7665 can be operated from a single 5 V supply and be interfaced to either digital logic housed in a 48-lead LQFP package or a 48-lead LFCSP package that com- bines space savings and flexible configurations as either serial or parallel interface ...
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... Values with REF = 2.5 V; with REF = 3 V, all values will scale linearly. 2 This is also the code for an overrange analog input. 3 This is also the code for an underrange analog input. TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7665. Different circuitry shown on this diagram is optional and is discussed below. ANALOG SUPPLY (5V ADR421 2 ...
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... R1 Except when using the 2.5 V analog input voltage range, the C AD7665 has to be driven by a very low impedance source to avoid S gain errors. That can be done by using a driver amplifier whose choice is eased by the primarily resistive analog input circuitry of the AD7665 ...
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... V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 5. The AD7665 is indepen- dent of power supply sequencing, once OVDD does not exceed DVDD by more than 0.3 V, and thus free from supply voltage induced latch-up ...
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... MODE ACQUIRE In Impulse Mode, conversions can be automatically initiated. If CNVST is held LOW when BUSY is LOW, the AD7665 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST LOW, the AD7665 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes LOW ...
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... BYTE PINS D[15:8] PINS D[7:0] SERIAL INTERFACE The AD7665 is configured to use the serial interface when the SER/PAR is held HIGH. The AD7665 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock ...
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... AD7665 CS CNVST BUSY t 29 SYNC t 14 SCLK t 15 SDOUT t 16 Figure 17. Master Serial Data Timing for Reading (Read after Convert) CS, RD CNVST BUSY t 17 SYNC SCLK t 18 SDOUT Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) ...
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... A discontinuous clock can be either normally HIGH or normally LOW when inactive. Figures 19 and 21 show the detailed timing diagrams of these methods. While the AD7665 is performing a bit decision important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particu- ...
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... Figure 22 shows an interface diagram between the AD7665 and an SPI-equipped microcontroller, such as the MC68HC11. To accommodate the slower speed of the microcontroller, the AD7665 acts as a slave device and data must be read after conver- sion. This mode also allows the daisy-chain feature. The convert command could be initiated in response to an internal timer interrupt ...
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... Digital and analog ground planes should be joined in only one place, preferably underneath the AD7665 least as close as possible to the AD7665. If the AD7665 system where multiple devices require analog-to- digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7665 ...
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... AD7665ASTZRL –40°C to +85°C AD7665ACPZ –40°C to +85°C AD7665ACPZRL –40°C to +85°C EVAL-AD7665CBZ RoHS Compliant Part. 2 The EVAL-AD7665CB can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 0.75 1.60 0.60 MAX 0.45 1 0.20 0.09 7° 3.5° ...
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... Edits to Circuit Information Section ........................................... 12 Edits to Table III ............................................................................. 13 New Voltage Reference Input Section ......................................... 15 Edits to ADSP-21065L in Master Serial Interface Section ........ 20 New ST-48 Package Outline ......................................................... 22 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. REV. C D01846-0-2/11(C) –23– AD7665 ...