AD1555 Analog Devices, AD1555 Datasheet

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AD1555

Manufacturer Part Number
AD1555
Description
24-Bit, 121 dB typical SNR, Sigma-Delta A/D converter with Integrated PGA
Manufacturer
Analog Devices
Datasheet

Specifications of AD1555

Resolution (bits)
24bit
# Chan
2
Sample Rate
256kSPS
Interface
Byte,Ser
Analog Input Type
Diff-Bip,SE-Bip
Ain Range
Bip 2.25V/(PGA Gain)
Adc Architecture
Sigma-Delta Modulator
Pkg Type
LCC

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Part Number
Manufacturer
Quantity
Price
Part Number:
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Analog Devices Inc
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Manufacturer:
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Quantity:
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a
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
GENERAL DESCRIPTION
The AD1555 is a complete sigma-delta modulator, combined
with a programmable gain amplifier intended for low frequency,
REV. B
AIN (+)
AIN (–)
TIN (+)
TIN (–)
FEATURES
AD1555
AD1556
APPLICATIONS
Seismic Data Acquisition Systems
Chromatography
Automatic Test Equipment
Fourth Order - Modulator
Large Dynamic Range
Low Input Noise: 80 nV rms @ 4 ms with
Low Distortion: –111 dB Max, –120 dB Typical
Low Intermodulation: 122 dB
Sampling Rate at 256 kSPS
Very High Jitter Tolerance
No External Antialias Filter Required
Programmable Gain Front End
Input Range:
Robust Inputs
Gain Settings: 1, 2.5, 8.5, 34, 128
Common-Mode Rejection (DC to 1 kHz)
77 mW Typical Low Power Dissipation
Standby Modes
FIR Digital Filter/Decimator
Serial or Parallel Selection of Configuration
Output Word Rates: 250 SPS to 16 kSPS
6.2 mW Typ Low Power Dissipation
70 W in Standby Mode
Reference Design and Evaluation Board with
116 dB Min, 120 dB Typical @ 1 ms
117 dB Typical @ 0.5 ms
Gain of 34,128
93 dB Min, 101 dB Typical @ Gain of 1
Software Available
AGND1
MUX
PGA
REFIN
PGAOUT
2.25 V
REF DIVIDER
REFCAP2
MODIN
AGND2
REFCAP1
DAC
AD1555
+V
FILTER
LOOP
A
AGND3
FUNCTIONAL BLOCK DIAGRAM
–V
A
MODE CONTROL
OVERVOLTAGE
DETECTION
GENERATION
LOGIC
CLOCK
V
L
DGND
high dynamic range measurement applications. The AD1555
outputs a ones-density bitstream proportional to the analog
input. When used in conjunction with the AD1556 digital filter/
decimator, a high performance ADC is realized.
The continuous-time analog modulator input architecture avoids
the need for an external antialias filter. The programmable gain
front end simplifies system design, extends the dynamic range,
and reduces the system board area. Low operating power and
standby modes makes the AD1555 ideal for remote battery-pow-
ered data acquisition systems.
The AD1555 is fabricated on Analog Devices’ BiCMOS process
that has high performance bipolar devices along with CMOS
transistors. The AD1555 and AD1556 are packaged, respectively,
in 28-lead PLCC and 44-lead MQFP packages and are specified
from –55°C to +85°C (AD1556 and AD1555 B Grade) and from
0°C to 85°C (AD1555 A Grade).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
CB0...CB4
MDATA
MFLG
MCLK
Figure 1. FFT Plot, Full-Scale AIN Input, Gain of 1
TDATA
CSEL
–100
–120
–140
–160
–180
–200
–20
–40
–60
–80
0
0
PGA0...PGA4
50
CONTROL
CLKIN SYNC
CLOCK DIVIDER
INPUT
PGA
MUX
100
150
with Low Noise PGA
CONFIGURATION
BW0...BW2 RESET PWRDN GND V
H/S
AD1555/AD1556
FREQUENCY – Hz
DIGITAL
200
FILTER
REGISTER
24-Bit - ADC
250
REGISTER
REGISTER
STATUS
DATA
300
ERROR
© Analog Devices, Inc., 2002
AD1556
350
INPUT SHIFT
REGISTER
f
SNR = 116.7dB
THD = –120.6dB
IN
OUTPUT
= 24.4Hz
DATA
400
MUX
www.analog.com
450
L
500
DIN
SCLK
CS
R/W
DOUT
DRDY
RSEL

Related parts for AD1555

AD1555 Summary of contents

Page 1

... CMOS transistors. The AD1555 and AD1556 are packaged, respectively, in 28-lead PLCC and 44-lead MQFP packages and are specified from –55°C to +85°C (AD1556 and AD1555 B Grade) and from 0°C to 85°C (AD1555 A Grade). FUNCTIONAL BLOCK DIAGRAM ...

Page 2

... –55 MIN MAX 2.990 –0.3 2.0 –10 – SINK = –2 mA 2.4 SOURCE –2– AGND = DGND = 0 V; MCLK = 256 kHz AD1555AP Typ Max Min Typ Max 120 116 120 119.5 115.5 119.5 117.5 114 117.5 109.5 104.5 109 – ...

Page 3

... Hz and 50 Hz, each 6 dB down full scale This specification is for the AD1555 only and does not include the errors from external components as, for instance, the external reference. 6 This offset specification is referred to the modulator output. ...

Page 4

... Input and Gain MODIN kHz (1 ms) 116 500 Hz (2 ms) 119 250 Hz (4 ms) 122 O * Not tested in production. Guaranteed by design. Table Ib. Minimum Dynamic Performances (AD1555BP Only) Input and Gain MODIN kHz (1 ms) 116 500 Hz (2 ms) 119 250 Hz (4 ms) 122 Not tested in production ...

Page 5

... The gain of the modulator is proportional to f CLKIN 2 With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor. Specifications subject to change without notice. REV 5%; –V = –5 V 5%; AD1555 CLKIN = 1.024 MHz; AGND = DGND = Symbol f CLKIN ...

Page 6

... TDATA t 10 RESET CLKIN SYNC DRDY ERROR Figure 4. AD1556 RESET, DRDY, and Overwrite Timings DATA VALID VALID Figure 3. AD1555/AD1556 Interface Timing –6– DATA VALID VALID REV. B ...

Page 7

... DOUT SCLK R SCLK t 31 MSB DIN REV. B MSB MSB– Figure 5. Serial Read Timing MSB–1 Figure 6. Serial Write Timing –7– AD1555/AD1556 HI-Z LSB+1 LSB LSB+1 LSB ...

Page 8

... AGND . . . . . . . . . . . . . . . . . . . . . . . – +0 DGND . . . . . . . . . . . . . . . . . . . . . . . . –0 Ground Voltage Differences DGND, AGND1, AGND2, AGND3 . . . . . . . . . . . ± 0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . –0 Internal Power Dissipation AD1555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 W AD1556 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 W Model AD1555AP AD1555APRL AD1555BP AD1555BPRL AD1556AS AD1556ASRL EVAL-AD1555/AD1556EB AD1555/56-REF *Contact factory for extended temperature range. ...

Page 9

... PGA1 3 PGA2 4 PGA3 5 AD1556 PGA4 6 TOP VIEW (Not to Scale) BW0 7 BW1 8 9 BW2 10 H CONNECT –9– AD1555/AD1556 REFIN REFCAP2 REFCAP1 AGND3 –V A – CLKIN 31 SYNC 30 TDATA 29 CSEL PWRDN ...

Page 10

... Modulator Control. These input pins control the mux selection, the PGA gain settings, and the standby modes of the AD1555. When used with the AD1556, these pins are generally directly tied to the CB0–CB4 output pins of the AD1556. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the PGA standby mode (refer to Table III) ...

Page 11

... CLKIN Clock Input. The clock input signal, nominally 1.024 MHz, provides the necessary clock for the AD1556. This clock frequency is divided by four to generate the MCLK signal for the AD1555. 35 MCLK Modulator Clock. Provides the modulator sampling clock frequency. The modulator always samples at one-fourth the CLKIN frequency ...

Page 12

... AD1555/AD1556 TERMINOLOGY DYNAMIC RANGE Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together in the bandwidth from the Nyquist frequency F value for dynamic range is expressed in decibels. SIGNAL-TO-NOISE RATIO (SNR) ...

Page 13

... TPC 5. Dynamic Range Distribution (272 Units) 150 f = 24.4Hz IN SNR = 68.2dB 140 THD = –120dB 130 120 110 100 90 3000 3500 4000 –55 TPC 6. Common-Mode Rejection vs. Temperature –13– AD1555/AD1556 2 8 128 –35 – 105 TEMPERATURE – C –121 –119 –117 –118 DYNAMIC RANGE – ...

Page 14

... AD1555/AD1556 –128 –120 –113 –105 CMRR – dB TPC 7. Common-Mode Rejection Distribution (272 Units) 120 G = 8.5 115 110 105 G = 128 G = 2.5 100 100 200 300 400 500 600 FREQUENCY – Hz TPC 8. Common-Mode Rejection vs. Frequency 0.20 0.15 0.10 0.05 0.00 –0.05 –0.10 –0.15 – ...

Page 15

... FREQUENCY – Hz TPC 14. AD1556 Pass Band Ripple, F REV. B 0.20 0.15 0.10 0.05 0.00 –0.05 –0.10 –0.15 –0.20 1500 2000 kHz (1/4 ms) TPC 15. AD1556 Pass Band Ripple 3000 4000 = 8 kHz (1/8 ms) O –15– AD1555/AD1556 4000 6000 8000 2000 FREQUENCY – kHz (1/16 ms) O ...

Page 16

... F The AD1555 operates from a dual analog supply (± 5 V), while the digital part of the AD1555 operates from supply. The AD1556 operates from a single 3 supply. Each device exhibits low power dissipation and can be configured for standby mode. ...

Page 17

... This combination allows accurate calibra- tion of the offset of the AD1555 for each gain setting. Also, a system noise calibration can be done using the internal 1 kΩ resistor as a noise reference. ...

Page 18

... Sigma-delta modulators have the potential to generate idle tones that occur for dc inputs close to ground. To prevent this unde- sirable effect, the AD1555 modulator offset is set to about –60 mV. In this manner, any existing idle tones are moved out of the band of interest and filtered out by the digital filter. ...

Page 19

... The AD1556 is a digital finite impulse response (FIR) linear phase low pass filter and serves as the decimation filter for the AD1555. It takes the output bitstream of the AD1555, filters and decimates user-selectable choice of seven different filters associated with seven decimation ratios, in power of 2 from 1/16 to 1/1024 ...

Page 20

... DIN, SCLK, CS, and R/W. In this mode, when RESET is active, the configuration register mimics the selec- tion of the hardware pins. The AD1556 and the AD1555 can be put in power-down by software. The DRDYBUF bit controls the operating mode of the DRDY output pin ...

Page 21

... This will re- duce the effect of feedthrough through the board. The power supply lines to the AD1555 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supplies impedance resent to the AD1555 and reduce the magnitude of the supply spikes ...

Page 22

... DB1 CB1 DB0 (LSB) CB0 The AD1555 has three different ground pins: AGND1, AGND2, and AGND3 plane, depending on the configuration. AGND1 should be a star point and be connected to the analog ground point. AGND2 should be directly tied to AGND1. A low impedance trace should connect in the following order: AGND3, the low side of the reference decoupling capacitor on REFCAP1, the ground of the reference voltage, and return to AGND1 ...

Page 23

... MAX SQ 0.390 (9.90) 0.041 (1.03) 0.029 (0.73 SEATING PLANE TOP VIEW (PINS DOWN) 11 0.010 (0.25 MAX 0.009 (0.23) 0.005 (0.13) 0.018 (0.45) 0.031 (0.80) BSC 0.012 (0.30) 0.083 (2.10) 0.077 (1.95) –23– AD1555/AD1556 0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64 0.315 (8.00) REF 23 ...

Page 24

–24– ...

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