AD7898 Analog Devices, AD7898 Datasheet
AD7898
Specifications of AD7898
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AD7898 Summary of contents
Page 1
... The part accepts an analog input range of ± (AD7898-10) and ± 2.5 V (AD7898-3), and operates from a single 5 V supply, consuming only 22.5 mW max. The part is available in an 8-lead Standard Small Outline Package (SOIC) ...
Page 2
... Intermodulation Distortion (IMD) 2nd Order Terms 3rd Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth–AD7898-10 Full Power Bandwidth–AD7898-3 Full Power Bandwidth–AD7898-10 Full Power Bandwidth–AD7898-3 DC ACCURACY Resolution Minimum Resolution for Which No Missing Codes are Guaranteed 2 Relative Accuracy 2 ...
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... SCLK to Data Valid Hold Time ns min SCLK Falling Edge to SDATA High Impedance ns max SCLK Falling Edge to SDATA High Impedance µs max Power-Up Time from Power-Down Mode DRIVE –3– AD7898 = unless otherwise A MIN MAX = 5 V ± 5% DRIVE = 5 V ± 5% DRIVE = 2 ...
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... V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0 Analog Input Voltage to GND AD7898- ± AD7898 ± Reference Input Voltage to GND . . . . –0 Digital Input Voltage to GND . . . . . . . –0 Digital Output Voltage to GND . . . . . –0 Operating Temperature Range Commercial (A, B Versions –40°C to +85°C Storage Temperature Range . . . . . . . . . . . – ...
Page 5
... SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7898. When in Mode 0 operation, a new serial data bit is clocked out on the falling edge of this serial clock. In Mode 0, data is guaranteed valid for 20 ns after this falling edge so that data can be accepted on the falling edge when a fast serial clock is used ...
Page 6
... N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6. 1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7898 defined as ...
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... PERFORMANCE CURVES TPC 1 shows a typical FFT plot for the AD7898 at 220 kSPS sampling rate with a 30 kHz input frequency while operating in Mode 0. 5 –15 –35 –55 –75 –95 –115 FREQUENCY – kHz TPC 1. Mode 0 Dynamic Performance TPC 2 shows a typical FFT plot for the AD7898 at 220 kSPS sampling rate with a 30 kHz input frequency while operating in Mode 1 ...
Page 8
... The A/D converter section of the AD7898 consists of a conventional successive-approximation converter based around an R-2R ladder structure. The signal scaling on the AD7898-10 and AD7898-3 allows the part to handle ± and ± 2.5 V input signals, respectively, while operating from a single 5 V supply 5.25V The part requires an external 2 ...
Page 9
... For the AD7898-10 kΩ 7.5 kΩ and kΩ. For the AD7898- 6.5 kΩ and R3 is open circuit. For the AD7898-10 and AD7898-3, the designed code transi- tions occur midway between successive LSB values (i ...
Page 10
... V and 5 V processors. For example, if the AD7898 were operated with and the V DD pin could be powered from supply. The AD7898 has good dynamic performance with while still being able to DD interface digital parts. Care should be taken to ensure ...
Page 11
... The 16 serial clock input does not have to be continuous during 5 the serial read operation. The 16 bits of data (four leading zeros and 12-bit conversion result) can be read from the AD7898 in a number of bytes. The AD7898 counts the serial clock edges to know which bit from the output register should be placed on the SDATA out- put ...
Page 12
... SCLK falling edge as shown in Figure 8. Sixteen serial clock cycles are required to perform the conver- sion process and to access data from the AD7898. CS going low provides the first leading zero to be read in by the micro- controller or DSP. The remaining data is then clocked out by ...
Page 13
... Figure 13 shows an interface between the AD7898 and the 8x51/L51 microcontroller. The 8x51/L51 is configured for its Mode 0 serial interface mode. The diagram shows the simplest form of the interface where the AD7898 is the only part con- nected to the serial port of the 8x51/L51 and, therefore, no decoding of the serial read operations is required. ...
Page 14
... AD7898. A simple AND function on this port bit and the serial clock from the 8x51/L51 will provide this function. The port bit should be high to select the AD7898 and low when it is not selected ...
Page 15
... DSP56xxx will provide equidistant sampling. The V pin of the AD7898 takes the same supply voltage as that DRIVE of the DSP56xxx. This allows the ADC to operate at a higher voltage than the serial interface, i.e., DSP56xxx, if necessary. ...
Page 16
... SIZE = 1. To implement the power-down modes with an 8-bit transfer set SIZE = 0. A connection diagram is shown in Figure 20. The V pin of the AD7898 takes the same sup- DRIVE ply voltage as that of the MC68HC16. This allows the ADC to operate at a higher voltage than the serial interface, i.e., MC68HC16, if necessary ...